Conversions - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

26.3.2 Conversions

A conversion consists of two phases: acquisition and approximation. The input is sampled in the acquisition phase before it is converted
to digital representation during the approximation phase. The acquisition time can be configured independently for scan sequence and
single channel conversions (see
can be set to 1 , 2, 3 or any integer power of 2 from 4 to 256 adc_clk_sar cycles.
Note:
For high impedance sources the acquisition time should be adjusted to allow enough time for the internal sample capacitor to fully
charge. The minimum acquisition time for sampling at 1 Msps and typical input loading is 187.5 ns.
The ADC uses one adc_clk_sar cycle per output bit in the approximation phase plus 1 extra adc_clk_sar cycle.
Where T is the acquisition time set by the AT bit field, N is the resolution (in bits), and OVSRSEL is the oversampling ratio according
acq
to the OVSRSEL field in ADCn_CTRL when oversampling is enabled (see
ADC_CLK
Conversion clock
ADC action
26.3.3 ADC Modes
The ADC contains two programmable modes: single channel mode and scan mode. Both modes have separate configuration registers
and a four-deep FIFO for conversion results. Both modes may be set up to run only once per trigger or to automatically repeat after
each operation. The scan mode has priority over the single channel mode. However by default, if scan sequence is running, a triggered
single channel conversion will be interleaved between two scan samples.
26.3.3.1 Single Channel Mode
Single channel mode can be used to convert a single channel either once per trigger or repetitively. The configuration of single channel
mode is done using the ADCn_SINGLECTRL and ADCn_SINGLECTRLX registers and the result FIFO can be read through the
ADCn_SINGLEDATA register. The DVL field of the ADCn_SINGLECTRLX controls the FIFO watermark crossing which sets the SIN-
GLEDV bit in ADCn_STATUS high and is cleared when the data is read and the number of unread data samples falls below the DVL
threshold. The user can choose to throw out new samples or overwrite the old samples when the FIFO becomes full by programming
the FIFOOFACT field of the ADCn_SINGLECTRLX register. Single channel results can also be read through ADCn_SINGLEDATAP
without popping the FIFO, returning its latest element. The DIFF field in ADCn_SINGLECTRL selects whether differential or single
ended inputs are used and POSSEL and NEGSEL selects the input signal(s). The CMPEN bit in the ADCn_SINGLECTRL register ena-
bles the window compare function, and the latest converted data is compared against values programmed into the ADGT and ADLT
fields of the ADCn_CMPTHR register and generates SINGLECMP interrupts if enabled. The window compare function allows for com-
pare triggering both within (if ADGT less than ADLT) or out of (if ADGT greater than ADLT) window.
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26.3.3 ADC Modes) by setting AT in ADCn_SINGLECTRL/ADCn_SCANCTRL. The acquisition times
T = (T + (N + 1) x T
conv acq
Figure 26.2. ADC Total Conversion Time Per Output
SINGLEAT/
Bit 11 Bit 10 Bit 9
SCANAT
Figure 26.3. ADC Conversion Timing
) x OVSRSEL
adc_clk_sar
26.3.10.6
Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
6-bit value ready 8-bit value ready
Reference Manual
ADC - Analog to Digital Converter
Oversampling).
Bit 3 Bit 2 Bit 1 Bit 0
12-bit value ready
Rev. 1.1 | 848