Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 311

even while the system is running on the HFRCO. Only write CMU_HFRCOCTRL when it is ready for an update as indicated by
HFRCOBSY=0 in CMU_SYNCBUSY.
Offset
0x010
Reset
Access
Name
Bit Name
31:28 VREFTC
Writing this field adjusts the temperature coefficient trim on comparator reference.
27 FINETUNINGEN
Settings this bit enables HFRCO fine tuning.
26:25 CLKDIV
Writing this field configures the HFRCO clock output divider.
Value
0
1
2
24 LDOHP
Settings this bit puts the HFRCO LDO in high power mode.
23:21 CMPBIAS
Writing this field adjusts the HFRCO comparator bias current.
20:16 FREQRANGE
Writing this field adjusts the HFRCO frequency range.
15:14 Reserved
13:8 FINETUNING
Writing this field adjusts the HFRCO fine tuning value. Higher value means lower frequency. Fine tuning is only enabled
when FINETUNINGEN is set.
7 Reserved
6:0 TUNING
Writing this field adjusts the HFRCO tuning value. Higher value means lower frequency.
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Reset Access Description
0xB RWH HFRCO Temperature Coefficient Trim on Comparator Reference
0 RWH Enable Reference for Fine Tuning
0x0 RWH Locally Divide HFRCO Clock Output
Mode Description
DIV1 Divide by 1.
DIV2 Divide by 2.
DIV4 Divide by 4.
1 RWH HFRCO LDO High Power Mode
0x2 RWH HFRCO Comparator Bias Current
0x08 RWH HFRCO Frequency Range
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x1F RWH HFRCO Fine Tuning Value
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x7F RWH HFRCO Tuning Value
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 311