Msc_Ien - Interrupt Enable Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

7.5.11 MSC_IEN - Interrupt Enable Register

Offset
0x03C
Reset
Access
Name
Bit Name
31:9 Reserved
8 LVEWRITE
Enable/disable the LVEWRITE interrupt
7 Reserved
6 WDATAOV
Enable/disable the WDATAOV interrupt
5 ICACHERR
Enable/disable the ICACHERR interrupt
4 PWRUPF
Enable/disable the PWRUPF interrupt
3 CMOF
Enable/disable the CMOF interrupt
2 CHOF
Enable/disable the CHOF interrupt
1 WRITE
Enable/disable the WRITE interrupt
0 ERASE
Enable/disable the ERASE interrupt
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW LVEWRITE Interrupt Enable
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW WDATAOV Interrupt Enable
0 RW ICACHERR Interrupt Enable
0 RW PWRUPF Interrupt Enable
0 RW CMOF Interrupt Enable
0 RW CHOF Interrupt Enable
0 RW WRITE Interrupt Enable
0 RW ERASE Interrupt Enable
Bit Position
Reference Manual
MSC - Memory System Controller
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 144