Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 496

17.3.9.1 Slave State Machine
The slave state machine is shown in
interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission pro-
ceed.
0/1
Idle/busy
Bus state/event
Transmitted by self
Received from master
Bus state (STATE)
Interrupt flag set
Interaction required. Clock-
stretching applied until
manual or automatic
interaction has been
performed
17.3.9.2 Address Recognition
2
The I C module provides automatic address recognition for 7-bit addresses. 10-bit address recognition is not fully automatic, but can be
assisted by the 7-bit address comparator as shown in
modes (except EM4).
The slave address, i.e., the address which the I
to the address, a mask must be specified, telling the address comparator which bits of an incoming address to compare with the ad-
dress defined in I2Cn_SADDR. The mask is defined in I2Cn_SADDRMASK, and for every zero in the mask, the corresponding bit in the
slave address is treated as a don't-care, i.e., the 0-masked bits are ignored.
An incoming address that fails address recognition is automatically replied to with a NACK. Since only the bits defined by the mask are
checked, a mask with a value 0x00 will result in all addresses being accepted. A mask with a value 0x7F will only match the exact
address defined in I2Cn_SADDR, while a mask 0x70 will match all addresses where the three most significant bits in I2Cn_SADDR and
the incoming address are equal.
If GCAMEN in I2Cn_CTRL is not set, the start-byte, i.e., the general call address with the R/W bit set is ignored unless it is included in
the defined slave address and and the address mask.
When an address is accepted by the address comparator, the decision of whether to ACK or NACK the address is passed to software.
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Figure 17.16 I2C Slave State Machine on page
Slave transmitter
S ADDR R
Slave receiver
ADDR W
Go to state
Figure 17.16. I2C Slave State Machine
17.3.11 Using 10-bit
2
C module should be addressed with, is defined in the I2Cn_SADDR register. In addition
I2C - Inter-Integrated Circuit Interface
496. The dotted lines show where I
73
A DATA
N
71 B1
A DATA
N
Addresses. Address recognition is supported in all energy
Reference Manual
2
C-specific
D5
A P 0
Sr 41
DD
N
Arb. lost 1
A P 0
Sr 41
N
X Arb. lost 1
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