Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 884

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Bit
Name
21
Reserved
20:17
PRSSEL
Select PRS trigger for single channel.
Value
0
1
2
3
4
5
6
7
8
9
10
11
16
PRSMODE
PRS trigger mode of single channel.
Value
0
1
15
Reserved
14
FIFOOFACT
Select how FIFO behaves when full
Value
0
1
13:12
DVL
Select single channel Data Valid level. SINGLE IRQ is set when (DVL+1) number of single channels have been converted
and their results are available in the Single FIFO.
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Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0
RW
Single Channel PRS Trigger Select
Mode
Description
PRSCH0
PRS ch 0 triggers single channel
PRSCH1
PRS ch 1 triggers single channel
PRSCH2
PRS ch 2 triggers single channel
PRSCH3
PRS ch 3 triggers single channel
PRSCH4
PRS ch 4 triggers single channel
PRSCH5
PRS ch 5 triggers single channel
PRSCH6
PRS ch 6 triggers single channel
PRSCH7
PRS ch 7 triggers single channel
PRSCH8
PRS ch 8 triggers single channel
PRSCH9
PRS ch 9 triggers single channel
PRSCH10
PRS ch 10 triggers single channel
PRSCH11
PRS ch 11 triggers single channel
0
RW
Single Channel PRS Trigger Mode
Mode
Description
PULSED
Single channel trigger is considered a regular asynchronous pulse that
starts ADC warm-up, then acquisition/conversion sequence. The
ADC_CLK controls the warmup-time.
TIMED
Single channel trigger should be a pulse long enough to provide the re-
quired warm-up time for the selected ADC warmup mode. The negative
edge requests sample acquisition. DELAY can be used to delay the
warm-up request if the pulse is too long.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0
RW
Single Channel FIFO Overflow Action
Mode
Description
DISCARD
FIFO stops accepting new data if full, triggers SINGLEOF IRQ.
OVERWRITE
FIFO overwrites old data when full, triggers SINGLEOF IRQ.
0x0
RW
Single Channel DV Level Select
Reference Manual
ADC - Analog to Digital Converter
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 884

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