Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 488

17.3.7.1 Master State Machine
The master state machine is shown in
the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when
arriving at the right side of the state machine.
Branches in the path through the state machine are the results of bus events and choices made by software, either directly or indirectly.
The dotted lines show where I
may be required by software to let the transmission proceed.
0/1
Idle/busy
Bus state/event
Transmitted by self
Received from slave
START
S
condition
Sr Repeated START condition
A ACK
Slave address + write
ADDR W
(R/W bit cleared)
Slave address + read
ADDR R
(R/W bit set)
Bus state (STATE)
Interrupt flag set
Interaction required. Wait-
states inserted until manual
or automatic interaction has
been performed
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Figure 17.15 I2C Master State Machine on page
2
C-specific interrupt flags are set along the path and the full-drawn circles show places where interaction
Master transmitter
57
Waiting
S ADDR W
for idle
STOP
P
Master receiver
condition
ADDR R
N NACK
Arbitration lost
ADDR R
ADDR W
Go to state ADDR X
Bus reset
P
Figure 17.15. I2C Master State Machine
I2C - Inter-Integrated Circuit Interface
488. A master operation starts in the far left of
97
A DATA A
9F N
N
Arb. lost
93 B3
A DATA
9B
N
Arb. lost, ADDR match 73
Arb. lost, ADDR match 71
Arb. lost, no match
Reference Manual
D7
P 0
Sr 57
DF
1
A P 0
Sr 57
N
X Arb. lost 1
Slave transmitter
Slave receiver
1
0
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