Debug Mode; Interrupts, Dma And Prs Output; Gpio Input/Output - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

20.3.4 Debug Mode

When the CPU is halted in debug mode, the timer can be configured to either continue to run or to be frozen. This is configured in
DEBUGRUN in TIMERn_CTRL.

20.3.5 Interrupts, DMA and PRS Output

The timer has 3 different types of output events:
• Counter Underflow
• Counter Overflow
• Compare match or input capture (one per Compare/Capture channel)
Each of the events has its own interrupt flag. Also, there is one interrupt flag for each Compare/Capture channel which is set on buffer
overflow in capture mode. Buffer overflow happens when a new capture pushes an old unread capture out of the TIMERn_CCx_CCV/
TIMERn_CCx_CCVB register pair.
If the interrupt flags are set and the corresponding interrupt enable bits in TIMERn_IEN are set high, the timer will send out an interrupt
request. Each of the events will also lead to a one HFPERCLK
LEVEL in TIMERn_CCx_CTRL will make the compare match PRS output follow the compare match output, instead of outputting one
HFPERCLK cycle high pulse. Interrupts are cleared by setting the corresponding bit in the TIMERn_IFC register.
TIMERn
Each of the events will also set a DMA request when they occur. The different DMA requests are cleared when certain acknowledge
conditions are met, see Table 20.4 TIMER/WTIMER DMA Events on page
interrupt flags. Software must still manually clear the interrupt flag if interrupts are in use.
If DMACLRACT is set in TIMERn_CTRL, the DMA request is cleared when the triggered DMA channel is active, without having to ac-
cess any timer registers. This is useful in cases where a timer event is used to trigger a DMA transfer that does not target the CCV or
CCVB register.
Underflow/Overflow
CC 0
CC 1
CC 2

20.3.6 GPIO Input/Output

The TIMn_CCx inputs/outputs and TIM0_CDTIx outputs are accessible as alternate functions through GPIO. Each pin connection can
be enabled/disabled separately by setting the corresponding CCxPEN or CDTIxPEN bits in TIMERn_ROUTE. The LOCATION bits in
the same register can be used to move all enabled pins to alternate pins. See the device data sheet for the mapping between block
locations (LOC0, LOC1, etc.) and actual device pins (PA0, PA1, etc.).
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Table 20.4. TIMER/WTIMER DMA Events
Event
cycle high pulse on individual PRS outputs. Setting PRSOCNF to
TIMERn
673. Events which clear the DMA requests do not clear
Acknowledge/Clear
Read or write to TIMERn_CNT or TIMERn_TOPB
Read or write to TIMERn_CC0_CCV or TIMERn_CC0_CCVB
Read or write to TIMERn_CC1_CCV or TIMERn_CC1_CCVB
Read or write to TIMERn_CC2_CCV or TIMERn_CC2_CCVB
Reference Manual
TIMER/WTIMER - Timer/Counter
Rev. 1.1 | 673