Bit
Name
Value
0
1
17.5.2 I2Cn_CMD - Command Register
Offset
0x004
Reset
Access
Name
Bit
Name
31:8
Reserved
7
CLEARPC
Set to clear pending commands.
6
CLEARTX
Set to clear transmit buffer and shift register. Will not abort ongoing transfer.
5
ABORT
Abort the current transmission making the bus go idle. When used in combination with STOP, a STOP condition is sent as
soon as possible before aborting the transmission. The stop condition is subject to clock synchronization.
4
CONT
Set to continue transmission after a NACK has been received.
3
NACK
Set to transmit a NACK the next time an acknowledge is required.
2
ACK
Set to transmit an ACK the next time an acknowledge is required.
1
STOP
Set to send stop condition as soon as possible.
0
START
Set to send start condition as soon as possible. If a transmission is ongoing and not owned, the start condition will be sent
as soon as the bus is idle. If the current transmission is owned by this module, a repeated start condition will be sent. Use
in combination with a STOP command to automatically send a STOP, then a START when the bus becomes idle.
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Reset
Access
Description
Description
The I
The I
Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0
W1
Clear Pending Commands
0
W1
Clear TX
0
W1
Abort Transmission
0
W1
Continue Transmission
0
W1
Send NACK
0
W1
Send ACK
0
W1
Send Stop Condition
0
W1
Send Start Condition
I2C - Inter-Integrated Circuit Interface
2
C module is disabled. And its internal state is cleared
2
C module is enabled.
Bit Position
Reference Manual
1.2 Conven-
Rev. 1.1 | 507
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