Leuartn_Cmd - Command Register (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

19.5.2 LEUARTn_CMD - Command Register (Async Reg)

For more information about asynchronous registers see
Offset
0x004
Reset
Access
Name
Bit Name
31:8 Reserved
7 CLEARRX
Set to clear receive buffer and the RX shift register.
6 CLEARTX
Set to clear transmit buffer and the TX shift register.
5 RXBLOCKDIS
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
4 RXBLOCKEN
Set to set RXBLOCK, resulting in all incoming frames being discarded.
3 TXDIS
Set to disable transmission.
2 TXEN
Set to enable data transmission.
1 RXDIS
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0 RXEN
Set to activate data reception on LEUn_RX.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 W1 Clear RX
0 W1 Clear TX
0 W1 Receiver Block Disable
0 W1 Receiver Block Enable
0 W1 Transmitter Disable
0 W1 Transmitter Enable
0 W1 Receiver Disable
0 W1 Receiver Enable
Bit Position
Reference Manual
Registers).
1.2 Conven-
Rev. 1.1 | 632