Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 258

Bit Name
11:8 PFETCNT
Low Noise mode PFET power switch count number. The selected number of switches are PFETCNT+1. Reset with POR,
Hard Pin Reset, or BOD Reset.
7:6 Reserved
5 LNFORCECCMIMM
When set, this bit allows software to change LNFORCECCM bit and have the change take effect while DCDC is running.
Otherwise, LNFORCECCM must be programmed prior to enabling the DCDC.
4:3 Reserved
2 LPCMPHYSHI
Reserved for internal use. Should always be set to 1.
1 LPCMPHYSDIS
Reserved for internal use. Should always be set to 1.
0 LNFORCECCM
When this bit is set to 0 in low noise mode, the zero detector is configured as zero-crossing detector and the DCDC will be
in forced CCM mode. The threshold set by ZDETILIMSEL will be ignored. When this bit is set to 1 in low noise mode, the
zero detector is configured as reverse-current limiter and the DCDC will be in DCM mode. The reverse current limit level is
set by ZDETILIMSEL. In low power mode, the zero detector is always configured as zero-crossing detector. Reset with
POR, Hard Pin Reset, or BOD reset.
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Reset Access Description
0x7 RW PFET Switch Number Selection
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Force DCDC Into CCM Mode Immediately, Based on LNFOR-
CECCM
To ensure compatibility with future devices, always write bits to 0. More information in
tions
1 RW Comparator Threshold on the High Side
1 RW Disable LP Mode Hysteresis in the State Machine Control
0 RW Force DCDC Into CCM Mode in Low Noise Operation
Reference Manual
EMU - Energy Management Unit
1.2 Conven-
1.2 Conven-
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