Emu_Dcdclncompctrl - Dcdc Low Noise Compensator Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

10.5.19 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register

Offset
0x058
Reset
Access
Name
Bit Name
31:28 COMPENC3
LN mode compensator C3 trim, 0.5pF-8pF in 0.5pF steps. Reset with POR, Hard Pin Reset, or BOD Reset.
27 Reserved
26:24 COMPENC2
LN mode compensator C2 trim, 1pF-8pF in 1pF steps. Reset with POR, Hard Pin Reset, or BOD Reset.
23:22 Reserved
21:20 COMPENC1
LN mode compensator C1 trim, 0.15pF-0.60pF in 0.15pF step. Reset with POR, Hard Pin Reset, or BOD Reset.
19:16 Reserved
15:12 COMPENR3
LN mode compensator r3 trim, 5-80KOhm in 5Khom steps. Reset with POR, Hard Pin Reset, or BOD Reset.
11:9 Reserved
8:4 COMPENR2
LN mode compensator r2 trim, 50-1600KOhm, in 50KOhm steps. Reset with POR, Hard Pin Reset, or BOD Reset.
3 Reserved
2:0 COMPENR1
LN mode compensator r1 trim, 500-1200kOhm, in 100KOhm steps. Reset with POR, Hard Pin Reset, or BOD Reset.
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Reset Access Description
0x5 RW Low Noise Mode Compensator C3 Trim Value
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x7 RW Low Noise Mode Compensator C2 Trim Value
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x2 RW Low Noise Mode Compensator C1 Trim Value
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x4 RW Low Noise Mode Compensator R3 Trim Value
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x07 RW Low Noise Mode Compensator R2 Trim Value
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x7 RW Low Noise Mode Compensator R1 Trim Value
Bit Position
Reference Manual
EMU - Energy Management Unit
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 261