I2C-Bus Overview - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

17.3.1 I2C-Bus Overview

2
The I C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in
Example on page 480. As a true multi-master bus it includes collision detection and arbitration to resolve situations where multiple
masters transmit data at the same time without data loss.
SDA
SCL
Each device on the bus is addressable by a unique address, and an I
masters.
Both the bus lines are open-drain. The maximum value of the pull-up resistor can be calculated as a function of the maximal rise-time tr
for the given bus speed, and the estimated bus capacitance Cb as shown in
The maximal rise times for 100 kHz, 400 kHz and 1 MHz I
Note:
The GPIO drive strength can be used to control slew rate.
Note:
If V drops below the voltage on SCL and SDA lines, the MCU could become back powered and pull the SCL and SDA lines low.
dd
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I 2 C master I 2 C master
#1 #2
Figure 17.2. I2C-Bus Example
Rp(max) = t
Figure 17.3. I2C Pull-up Resistor Equation
2
I 2 C slave I 2 C slave I 2
#1 #2
2
C master can address all the devices on the bus, including other
Figure 17.3 I2C Pull-up Resistor Equation on page
/ (0.8473 x Cb)
r
C are 1 µs, 300 ns and 120 ns respectively.
I2C - Inter-Integrated Circuit Interface
Figure 17.2 I2C-Bus
V
DD
C slave
R
p
#3
Reference Manual
480.
Rev. 1.1 | 480