I2Cn_Clkdiv - Clock Division Register; I2Cn_Saddr - Slave Address Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

17.5.5 I2Cn_CLKDIV - Clock Division Register

Offset
0x010
Reset
Access
Name
Bit Name
31:9 Reserved
8:0 DIV
Specifies the clock divider for the I

17.5.6 I2Cn_SADDR - Slave Address Register

Offset
0x014
Reset
Access
Name
Bit Name
31:8 Reserved
7:1 ADDR
Specifies the slave address of the device.
0 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x000 RW Clock Divider
2
C. Note that DIV must be 1 or higher when slave is enabled.
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x00 RW Slave Address
To ensure compatibility with future devices, always write bits to 0. More information in
tions
I2C - Inter-Integrated Circuit Interface
Bit Position
Bit Position
Reference Manual
1.2 Conven-
1.2 Conven-
1.2 Conven-
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