30.5.10 TRNGn_INITWAITVAL - Initial Wait Counter
Offset
0x034
Reset
Access
Name
Bit
Name
31:8
Reserved
7:0
VALUE
Number of clock cycles to wait before sampling data from the noise source.
30.5.11 TRNGn_FIFO - FIFO Data (Actionable Reads)
Offset
0x100
Reset
Access
Name
Bit
Name
31:0
VALUE
Data may be read from the FIFO 32 bits at a time using this register.
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Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0xFF
RW
Wait counter value
Reset
Access
Description
0x00000000
R
FIFO Read Data
TRNG - True Random Number Generator
Bit Position
Bit Position
Reference Manual
1.2 Conven-
Rev. 1.1 | 1023
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