Eration - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

26.5.12 ADCn_BIASPROG - Bias Programming Register for Various Analog Blocks Used in ADC Operation
Offset
0x030
Reset
Access
Name
Bit Name
31:17 Reserved
16 GPBIASACC
Select bias accuracy mode for ADC operation. For devices with multiple ADCs, the bias will use the high accuracy setting
unless all ADC instances configure GPBIASACC to LOWACC.
Value
0
1
15:13 Reserved
12 VFAULTCLR
Use this bit to request clearing of the VREFOF flag. If VREFOF irq is enabled and is triggered, the user must set this bit in
the ISR to clear VREFOF. The user needs to reset this bit to enable VREFOF to trigger further IRQs upon VREF overflow
conditions.
11:4 Reserved
3:0 ADCBIASPROG
These bits are used to adjust the bias current in ADC analog block.
Value
0
4
8
12
14
15
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Accuracy Setting for the System Bias During ADC Operation
Mode Description
HIGHACC High accuracy setting. Use when configured for an internal VBGR ref-
erence source.
LOWACC Low accuracy setting. Can be used for all references other than VBGR
to conserve energy.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Clear VREFOF Flag
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Bias Programming Value of Analog ADC Block
Mode Description
NORMAL Normal power (use for 1Msps operation)
SCALE2 Scaling bias to 1/2
SCALE4 Scaling bias to 1/4
SCALE8 Scaling bias to 1/8
SCALE16 Scaling bias to 1/16
SCALE32 Scaling bias to 1/32
Bit Position
Reference Manual
ADC - Analog to Digital Converter
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 900