Usartn_Cmd - Command Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

18.5.4 USARTn_CMD - Command Register

Offset
0x00C
Reset
Access
Name
Bit Name
31:12 Reserved
11 CLEARRX
Set to clear receive buffer and the RX shift register.
10 CLEARTX
Set to clear transmit buffer and the TX shift register.
9 TXTRIDIS
Disables tristating of the transmitter output.
8 TXTRIEN
Tristates the transmitter output.
7 RXBLOCKDIS
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
6 RXBLOCKEN
Set to set RXBLOCK, resulting in all incoming frames being discarded.
5 MASTERDIS
Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.
4 MASTEREN
Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1.
To enable both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.
3 TXDIS
Set to disable transmission.
2 TXEN
Set to enable data transmission.
1 RXDIS
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0 RXEN
Set to activate data reception on U(S)n_RX.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 W1 Clear RX
0 W1 Clear TX
0 W1 Transmitter Tristate Disable
0 W1 Transmitter Tristate Enable
0 W1 Receiver Block Disable
0 W1 Receiver Block Enable
0 W1 Master Disable
0 W1 Master Enable
0 W1 Transmitter Disable
0 W1 Transmitter Enable
0 W1 Receiver Disable
0 W1 Receiver Enable
Bit Position
Reference Manual
1.2 Conven-
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