Cmu_Adcctrl - Adc Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.5.44 CMU_ADCCTRL - ADC Control Register

Offset
0x15C
Reset
Access
Name
Bit Name
31:9 Reserved
8 ADC0CLKINV
This bit enables inverting the selected clock to ADC0.
7:6 Reserved
5:4 ADC0CLKSEL
This bit controls which clock is used for ADC0 in case ADCCLKMODE in ADCn_CTRL is set to ASYNC. It should only be
changed when ADCCLKMODE in ADCn_CTRL is set to SYNC. HFXO should never be selected as clock source for ADC0
when disabling the HFXO (e.g. because of EM2 entry).
Value
0
1
2
3
3:0 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RWH Invert Clock Selected By ADC0CLKSEL
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RWH ADC0 Clock Select
Mode Description
DISABLED ADC0 is not clocked
AUXHFRCO AUXHFRCO is clocking ADC0
HFXO HFXO is clocking ADC0
HFSRCCLK HFSRCCLK is clocking ADC0
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
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