Cmu_Ifc - Interrupt Flag Clear Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.5.24 CMU_IFC - Interrupt Flag Clear Register

Offset
0x0A8
Reset
Access
Name
Bit Name
31 CMUERR
Write 1 to clear the CMUERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags
(This feature must be enabled globally in MSC.).
30 Reserved
29 ULFRCOEDGE
Write 1 to clear the ULFRCOEDGE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
28 LFRCOEDGE
Write 1 to clear the LFRCOEDGE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
27 LFXOEDGE
Write 1 to clear the LFXOEDGE interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
26:15 Reserved
14 LFTIMEOUTERR
Write 1 to clear the LFTIMEOUTERR interrupt flag. Reading returns the value of the IF and clears the corresponding inter-
rupt flags (This feature must be enabled globally in MSC.).
13 HFRCODIS
Write 1 to clear the HFRCODIS interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt
flags (This feature must be enabled globally in MSC.).
12 HFXOSHUNTOPTR-
DY
Write 1 to clear the HFXOSHUNTOPTRDY interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
11 HFXOPEAKDETRDY 0
Write 1 to clear the HFXOPEAKDETRDY interrupt flag. Reading returns the value of the IF and clears the corresponding
interrupt flags (This feature must be enabled globally in MSC.).
silabs.com | Building a more connected world.
Reset Access Description
0 (R)W1 Clear CMUERR Interrupt Flag
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 (R)W1 Clear ULFRCOEDGE Interrupt Flag
0 (R)W1 Clear LFRCOEDGE Interrupt Flag
0 (R)W1 Clear LFXOEDGE Interrupt Flag
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 (R)W1 Clear LFTIMEOUTERR Interrupt Flag
0 (R)W1 Clear HFRCODIS Interrupt Flag
0 (R)W1 Clear HFXOSHUNTOPTRDY Interrupt Flag
(R)W1 Clear HFXOPEAKDETRDY Interrupt Flag
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 340