Usartn_I2Sctrl - I2S Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

18.5.23 USARTn_I2SCTRL - I2S Control Register

Offset
0x05C
Reset
Access
Name
Bit Name
31:11 Reserved
10:8 FORMAT
Configure the data-width used internally for I2S data
Value
0
1
2
3
4
5
6
7
7:5 Reserved
4 DELAY
Set to add a one-cycle delay between a transition on the word-clock and the start of the I2S word. Should be set for stand-
ard I2S format
3 DMASPLIT
When set DMA requests for right-channel data are put on the TXBLRIGHT and RXDATAVRIGHT DMA requests.
2 JUSTIFY
Determines whether the I2S data is left or right justified
Value
0
1
1 MONO
Switch between stereo and mono mode. Set for mono
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW I2S Word Format
Mode Description
W32D32 32-bit word, 32-bit data
W32D24M 32-bit word, 32-bit data with 8 lsb masked
W32D24 32-bit word, 24-bit data
W32D16 32-bit word, 16-bit data
W32D8 32-bit word, 8-bit data
W16D16 16-bit word, 16-bit data
W16D8 16-bit word, 8-bit data
W8D8 8-bit word, 8-bit data
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Delay on I2S Data
0 RW Separate DMA Request for Left/Right Data
0 RW Justification of I2S Data
Mode Description
LEFT Data is left-justified
RIGHT Data is right-justified
0 RW Stero or Mono
Bit Position
Reference Manual
1.2 Conven-
1.2 Conven-
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