Silicon Laboratories EFR32xG21 Wireless Gecko Reference Manual

Silicon Laboratories EFR32xG21 Wireless Gecko Reference Manual

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EFR32xG21 Wireless Gecko
Reference Manual
The EFR32xG21 Wireless Gecko SoC is the first device in the Series 2 Wireless Gecko
Portfolio, and includes the EFR32MG21 Mighty Gecko and EFR32BG21 Blue Gecko.
The EFR32xG21 improves processing capability with a Cortex M33 core and has best in
class link budget while providing for lower active current for both the MCU and radio. The
dedicated security core (Secure Element) provides improved cryptography and hardware
security that is isolated from the main application CPU. This high performance and se-
cure multi-protocol device supports Zigbee, Thread, and Bluetooth 5.0.
The single-die solution provides industry-leading energy efficiency, processing capability,
and RF performance in a small form factor for IoT connected applications.
Core / Memory
TM
ARM Cortex
M33 processor
with DSP extensions,
FPU and Trust Zone
ETM
Debug Interface
Radio Transceiver
RF Frontend
I
LNA
Q
PGA
PA
Frequency
PA
Lowest power mode with peripheral operational:
EM0—Active
silabs.com | Building a more connected world.
Flash Program
Memory
LDMA
RAM Memory
Controller
Peripheral Reflex System
DEMOD
IFADC
AGC
Synth
MOD
EM1—Sleep
Clock Management
HF Crystal
HF
Fast Startup
Oscillator
RC Oscillator
RC Oscillator
EM23 HF RC
Oscillator
LF Crystal
Ultra LF RC
Oscillator
Oscillator
RC Oscillator
32-bit bus
Serial
I/O Ports
Interfaces
External
USART
Interrupts
General
I
2
C
Purpose I/O
Pin Reset
Pin Wakeup
EM2—Deep Sleep
KEY FEATURES
• 32-bit ARM® Cortex M33 core with 80
MHz maximum operating frequency
• Scalable Memory and Radio configuration
options available in QFN packaging
• Peripheral Reflex System enabling
autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Multiple Integrated 2.4 GHz PAs with up to
20 dBm transmit power
Energy
Management
Crypto Acceleration
Voltage
Regulator
Number Generator
Brown-Out
Detector
LF
Power-On Reset
Timers and Triggers
Timer/Counter
Protocol Timer
Low Energy Timer
Watchdog Timer
Real Time
Capture Counter
Back-Up Real
Time Counter
EM3—Stop
Security
True Random
Secure Debug
Authentication
Secure Element
Analog I/F
iADC
Analog
Comparator
EM4—Shutoff
Rev. 0.4

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Summary of Contents for Silicon Laboratories EFR32xG21 Wireless Gecko

  • Page 1 EFR32xG21 Wireless Gecko Reference Manual The EFR32xG21 Wireless Gecko SoC is the first device in the Series 2 Wireless Gecko KEY FEATURES Portfolio, and includes the EFR32MG21 Mighty Gecko and EFR32BG21 Blue Gecko. The EFR32xG21 improves processing capability with a Cortex M33 core and has best in •...
  • Page 2: Table Of Contents

    Table of Contents 1. About This Document ......22 1.1 Introduction .......22 1.2 Conventions .
  • Page 3 5.1 Introduction .......49 6. MSC - Memory System Controller ..... . 50 6.1 Introduction .
  • Page 4 6.8.10 MSC_USERDATASIZE - user data regsion size ....119 6.8.11 MSC_CMD - Command Register ..... 120 6.8.12 MSC_LOCK - Configuration Lock Register .
  • Page 5 8.5.3 CMU_LOCK - Configuration Lock Register ....151 8.5.4 CMU_WDOGLOCK - WDOG Configuration Lock Register ... . . 151 8.5.5 CMU_IF - Interrupt Flag Register .
  • Page 6 9.6.1 Introduction ......207 9.6.2 Features ......207 9.6.3 Functional Description .
  • Page 7 10.5.16 SMU_ESAURTYPES0 - Region Types 0 ....239 10.5.17 SMU_ESAURTYPES1 - Region Types 1 ....239 10.5.18 SMU_ESAUMRB01 - Movable Region Boundary .
  • Page 8 12.5.13 EMU_RSTCAUSE - Reset cause ....2 78 12.5.14 EMU_DGIF - Interrupt Flags Debug ....279 12.5.15 EMU_DGIEN - Interrupt Enables Debug .
  • Page 9 13.5.31 PRS_CONSUMER_SE_TAMPERSRC4 - SE TAMPERSRC4 Consumer Selection . . . 322 13.5.32 PRS_CONSUMER_SE_TAMPERSRC5 - SE TAMPERSRC5 Consumer Selection . . . 323 13.5.33 PRS_CONSUMER_SE_TAMPERSRC6 - SE TAMPERSRC6 Consumer Selection . . . 323 13.5.34 PRS_CONSUMER_SE_TAMPERSRC7 - SE TAMPERSRC7 Consumer Selection .
  • Page 10 13.5.79 PRS_CONSUMER_WDOG1_SRC1 - WDOG1 SRC1 Consumer Selection ..346 14. GPCRC - General Purpose Cyclic Redundancy Check ....347 14.1 Introduction......347 14.2 Features .
  • Page 11 15.5.8 RTCC_PRECNT - Pre-Counter Value Register ....376 15.5.9 RTCC_CNT - Counter Value Register ....377 15.5.10 RTCC_COMBCNT - Combined Pre-Counter and Counter Valu...
  • Page 12 18.3 Functional Description ......398 18.3.1 Internal Overview ......399 18.3.2 Free Running Mode .
  • Page 13: Single Descriptor Looped Transfer

    19.3.2 Counter Modes ......431 19.3.3 Compare/Capture Channels ..... . 437 19.3.4 Dead-Time Insertion Unit .
  • Page 14 20.3.9 DMA Support ......510 20.3.10 Timer ......511 20.3.11 Interrupts .
  • Page 15 21.3.10 Slave Operation ......576 21.3.11 Transfer Automation ......580 21.3.12 Using 10-bit Addresses .
  • Page 16 22.5.5 ACMP_INPUTCTRL - Input Control Register ....613 22.5.6 ACMP_STATUS - Status Register ....6 18 22.5.7 ACMP_IF - Interrupt Flag Register .
  • Page 17 24.1 Introduction ......6 77 24.2 Features ......678 24.3 Functional Description .
  • Page 18 24.6.30 GPIO_DBGROUTEPEN - Debugger Route Pin enable ... . .742 24.6.31 GPIO_TRACEROUTEPEN - Trace Route Pin Enable ... . . 743 24.6.32 GPIO_ACMP0_ROUTEEN - ACMP0 pin enable .
  • Page 19 24.6.78 GPIO_TIMER0_CC0ROUTE - CC0 port/pin select ....769 24.6.79 GPIO_TIMER0_CC1ROUTE - CC1 port/pin select ....769 24.6.80 GPIO_TIMER0_CC2ROUTE - CC2 port/pin select .
  • Page 20 25. LDMA - Linked DMA ......7 95 25.1 Introduction......795 25.1.1 Features .
  • Page 21: Ldma Source Selection Details

    25.7.19 LDMA_LINKLOAD - DMA Channel Link Load Register ... . .838 25.7.20 LDMA_REQCLEAR - DMA Channel Request Clear Register ...838 25.7.21 LDMA_IF - Interrupt Flag Register .
  • Page 22: About This Document

    Reference Manual About This Document 1. About This Document 1.1 Introduction This document contains reference material for the EFR32xG21 devices. All modules and peripherals in the EFR32xG21 devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such differences, including pinout, are covered in the device data sheets.
  • Page 23: Conventions

    Reference Manual About This Document 1.2 Conventions Register Names Register names are given with a module name prefix followed by the short register name: TIMERn_CTRL - Control Register The "n" denotes the module number for modules which can exist in more than one instance. Some registers are grouped which leads to a group name following the module prefix: GPIO_Px_DOUT - Port Data Out Register The "x"...
  • Page 24: Related Documentation

    Reference Manual About This Document Reset Value The reset value denotes the value after reset. Registers denoted with X have unknown value out of reset and need to be initialized before use. Note that read-modify-write operations on these registers before they are initialized results in undefined register values. Pin Connections Pin connections are given with a module prefix followed by a short pin name: CMU_CLKOUT1 (Clock management unit, clock output pin number 1)
  • Page 25: System Overview

    Reference Manual System Overview 2. System Overview Quick Facts What? The EFR32 Wireless Gecko is a highly integrated, configurable and low power wireless System-on- Chip (SoC) with a robust set of MCU and radio pe- ripherals. Why? The Radio enables support for Bluetooth Smart (BLE), ZigBee, Thread and Proprietary Protocols in 2.4 GHz frequency bands while the MCU system al- lows customized protocols and applications to run...
  • Page 26: Introduction

    Reference Manual System Overview 2.1 Introduction The high level features of EFR32xG21 include: • High performance radio transceiver • Low power consumption in transmit, receive, and standby modes • Excellent receiver performance, including sensitivity, selectivity, and blocking • Excellent transmitter performance, including programmable output power, low phase noise, and power-amplifier (PA) ramping •...
  • Page 27: Mcu Features Overview

    Reference Manual System Overview 2.3 MCU Features overview • ARM Cortex-M33 CPU platform • High Performance 32-bit processor @ up to 80 MHz • DSP instruction support and floating-point unit • Memory Protection Unit • Wake-up Interrupt Controller • Flexible Energy Management System •...
  • Page 28 Reference Manual System Overview • Timers/Counters • 2 × 16-bit Timer/Counter (TIMER) • Up to 3 Compare/Capture/PWM channels • Dead-Time Insertion • 32-bit Timer/Counter (TIMER) • Up to 3 Compare/Capture/PWM channels • 24-bit Low Energy Timer (LETIMER) • 32-bit Ultra Low Energy Backup Real Time Counter (BURTC) for periodic wake-up from any Energy Mode •...
  • Page 29: Oscillators And Clocks

    Reference Manual System Overview 2.4 Oscillators and Clocks EFR32xG21 has seven different oscillators integrated, as shown in Table 2.1 EFR32xG21 Oscillators on page Table 2.1. EFR32xG21 Oscillators Oscillator Frequency Optional? External Description components HFXO 38 MHz - 40 MHz Crystal High accuracy, low jitter high frequency crystal oscillator.
  • Page 30: Transmit Mode

    Reference Manual System Overview 2.7 Transmit Mode In transmit mode EFR32xG21 performs the following functionality: • Automatic PA power ramping during the start and end of a frame transmit • Programmable output power • Optional preamble and synchronization word insertion •...
  • Page 31: Hardware Crc Support

    Reference Manual System Overview 2.12 Hardware CRC Support EFR32xG21 supports a configurable CRC generation in transmit and verification in receive mode: • 8, 16, 24 or 32 bit CRC value • Configurable polynomial and initialization value • Optional inversion of CRC value over air •...
  • Page 32: Data Encryption And Authentication

    Reference Manual System Overview 2.15 Data Encryption and Authentication EFR32xG21 has hardware support for AES encryption, decryption and authentication modes. These security operations can be per- formed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits. AES modes of operations directly supported by the EFR32xG21 hardware are listed in Table 2.2 AES modes of operation with hard- ware support on page...
  • Page 33: Timers

    Reference Manual System Overview 2.16 Timers EFR32xG21 includes multiple timers, as can be seen from Table 2.3 EFR32xG21 Timers Overview on page Table 2.3. EFR32xG21 Timers Overview Timer Number of instances Typical clock source Overview RTCC Low frequency (LFXO or 32 bit Real Time Counter and LFRCO) Compare, typically used to ac-...
  • Page 34: System Processor

    Reference Manual System Processor 3. System Processor Quick Facts What? The EFR32xG21 features the industry leading Cor- tex-M33 CPU from ARM. Why? The ARM Cortex-M33 is designed for exceptionally short response time, high code density, and high 32- bit throughput while maintaining a strict cost and CM33 Core power consumption budget.
  • Page 35: Features

    Reference Manual System Processor 3.2 Features • Harvard architecture • Separate data and program memory buses (No memory bottleneck as in a single bus system) • 3-stage pipeline • Thumb-2 instruction set • Enhanced levels of performance, energy efficiency, and code density •...
  • Page 36: Interrupt Operation

    Reference Manual System Processor 3.3.1 Interrupt Operation Module Cortex-M NVIC IEN[n] Register SETENA[n]/CLRENA[n] Write Active interrupt Interrupt clear Interrupt request IF[n] condition clear SETPEND[n]/CLRPEND[n] Software generated interrupt Figure 3.1. Interrupt Operation The interrupt request (IRQ) lines are connected to the Cortex-M33. Each of these lines (shown in 3.3.3 Interrupt Request lines (IRQ)) is connected to one or more interrupt flags in one or more modules.
  • Page 37: Interrupt Request Lines (Irq)

    Reference Manual System Processor 3.3.3 Interrupt Request lines (IRQ) This table shows all IRQ's for the system processor. M33 High Speed interrupts are indicated by an '*'. See the individual peripheral chapters for more information on interrupt function. IRQ # Name Source(s) SETAMPERHOST...
  • Page 38 Reference Manual System Processor IRQ # Name Source(s) FRC.MAIN MODEM MODEM.MAIN PROTIMER PROTIMER.MAIN RAC_RSM RAC.RSM RAC_SEQ RAC.SEQ PRORTC PRORTC.MAIN SYNTH SYNTH.MAIN ACMP0 ACMP0.MAIN ACMP1 ACMP1.MAIN WDOG0 WDOG0.MAIN WDOG1 WDOG1.MAIN HFXO00 HFXO0.MAIN HFRCO0 HFRCO0.MAIN HFRCOEM23 HFRCOEM23.MAIN CMU.MAIN RADIOAES.MAIN IADC IADC0.MAIN MSC.irq_imem DPLL0 DPLL0.MAIN SYSCFG.SW0...
  • Page 39: Memory And Bus System

    Reference Manual Memory and Bus System 4. Memory and Bus System Quick Facts What? A low latency memory system including low energy Flash and RAM with data retention which makes the low energy modes attractive. Why? RAM retention reduces the need for storing data in Flash and enables frequent use of the ultra low en- ergy modes EM2 and EM3.
  • Page 40: Functional Description

    Reference Manual Memory and Bus System 4.2 Functional Description The internal memory segments of the Cortex-M33 are mapped into the system memory map as shown by Figure 4.1 System Address Space with Core and Code Space Listing on page Figure 4.1. System Address Space with Core and Code Space Listing Flash for the main program memory (CODE) is located at address 0x00000000 in the memory map of the EFR32xG21.
  • Page 41: Bus Matrix

    Reference Manual Memory and Bus System 4.2.1 Bus Matrix A multilayer AMBA AHB bus matrix connects the master bus interfaces to the AHB slaves. The bus matrix allows several AHB slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix.
  • Page 42: Flash

    Reference Manual Memory and Bus System 4.2.2 Flash The Flash retains data in any state and typically stores the application code and special user data. The Flash memory is typically pro- grammed through the debug interface, but can also be erased and written to from software. •...
  • Page 43 Reference Manual Memory and Bus System 4.2.4.1 Peripheral Map This table shows the address range for each peripheral. In addition it shows the lowest energy mode in which the peripheral is pow- ered. Note that EM3 is defined as EM2 with all clocks disabled. Therefore all peripherals powered in EM2 are also powered in EM3 but may not function if they require a running clock.
  • Page 44 Reference Manual Memory and Bus System Address Range Module Name Power Domain 0x4A004000 - 0x4A007FFF IADC0 EM2.B 0x4A008000 - 0x4A00BFFF ACMP0 EM2.B 0x4A00C000 - 0x4A00FFFF ACMP1 EM2.B 0x4A010000 - 0x4A013FFF I2C0 EM2.B 0x4A014000 - 0x4A017FFF HFRCOEM23 EM2.B 0x4A018000 - 0x4A01BFFF WDOG0 EM2.B 0x4A01C000 - 0x4A01FFFF...
  • Page 45 Reference Manual Memory and Bus System Address Range Module Name Power Domain 0x54000000 - 0x54003FFF RADIOAES_NS 0x54004000 - 0x54007FFF BUFC_NS 0x54008000 - 0x5400BFFF SMU_NS 0x58000000 - 0x58003FFF RTCC_NS EM2.A 0x5A000000 - 0x5A003FFF LETIMER0_NS EM2.B 0x5A004000 - 0x5A007FFF IADC0_NS EM2.B 0x5A008000 - 0x5A00BFFF ACMP0_NS EM2.B 0x5A00C000 - 0x5A00FFFF...
  • Page 46 Reference Manual Memory and Bus System 4.2.4.3 Peripheral Bit Set and Clear The EFR32xG21 supports bit set, bit clear, and bit toggle access to most peripheral registers. The bit set and bit clear functionality (also called Bit Access) enables modification of bit fields without the need to perform a read-modify-write. Also, the operation is contained within a single bus access.
  • Page 47 See EFR32xG21 Wireless Gecko for more information on on-demand clock sources. Disabling a high frequency module will stall the CPU until all pending SYNC writes have completed and any pending enable has com- pleted.
  • Page 48: Radio Transceiver

    Reference Manual Radio Transceiver 5. Radio Transceiver Quick Facts What? The Radio Transceiver provides access to transmit and receive data, radio settings and control inter- face. Why? The Radio Transceiver enables the user to commu- nicate using a wide range of data rates, modulation and frame formats.
  • Page 49: Introduction

    Reference Manual Radio Transceiver 5.1 Introduction The Radio Transceiver of the EFR32 Series 2 enables the user to control a wide range of settings and options for tailoring radio opera- tion precisely to the users need. It provides access to the transmit and receive data buffers and supports both dynamic and static frame lengths, as well as automatic address filtering and CRC insertion/verification.
  • Page 50: Msc - Memory System Controller

    Reference Manual MSC - Memory System Controller 6. MSC - Memory System Controller Quick Facts What? The user can perform Flash memory read, read con- figuration, and write operations through the Memory System Controller (MSC). SRAM operation may be configured though System Configuration (SYSCFG). Why? 01000101011011100110010101110010 The MSC allows the application code, user data,...
  • Page 51: Features

    Reference Manual MSC - Memory System Controller 6.2 Features • AHB read interface • Scalable access performance to optimize the Cortex-M33 code interface • Advanced energy optimization functionality • Conditional branch target prefetch suppression • Cortex-M33 disfolding of if-then (IT) blocks •...
  • Page 52: Instruction Cache

    Reference Manual MSC - Memory System Controller 6.3.2 Instruction Cache The instruction cache improves the speed and power consumption of the Cortex-M33 by providing fast low power access to recently executed instructions. For detailed information see 6.5 ICACHE - Instruction Cache 6.3.3 Device Information (DI) Page This read-only page holds calibration data from the production test, several unique device IDs, and other part specific information.
  • Page 53: Wait-States

    Reference Manual MSC - Memory System Controller 6.3.8 Wait-states Since the CPU may be clocked faster than the Flash can respond it is necessary to configure wait-states for flash accesses at higher CPU clock speeds. See the device Datasheet for information on the maximum allowed frequency for each wait-state setting. To config- ure the flash wait-states set the MODE field in MSC_READCTRL.
  • Page 54: Erase And Write Operations

    Reference Manual MSC - Memory System Controller 6.3.11 Erase and Write Operations The 20 MHz FSRCO is used for timing during flash write and erase operations. The default values in MSC_FLASHPROGRAMTIME and MSC_FLASHERASETIME contain the recommended programming configuration. To erase a page first set WREN in MSC_WRITECTRL and load any address in the page to be erased into the MSC_ADDRB register. Next check INVADDR, LOCKED, and WREADY in MSC_STATUS to ensure that the address is valid, not locked, and the MSC is ready to modify flash.
  • Page 55: Devinfo - Device Info Page

    Reference Manual MSC - Memory System Controller 6.3.11.2 Flash Lock The ability to program or erase pages may be disabled using the MSC_PAGELOCKWORDn registers. The bits in these registers may only be set by the CPU and are cleared when the device is reset. This means that once locked a page may not be unlocked until a reset occurs.
  • Page 56: Register Map

    Reference Manual MSC - Memory System Controller 6.4.1 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DEVINFO_INFO DI Information 0x004 DEVINFO_PART Part Info 0x008 DEVINFO_MEMINFO Memory Info 0x00C DEVINFO_MSIZE Memory Size 0x010 DEVINFO_PKGINFO Misc Device Info...
  • Page 57: Register Description

    Reference Manual MSC - Memory System Controller Offset Name Type Description 0x198 DEVINFO_IADC0HISPDOFF- IADC Offset Calibration SETCAL1 0x1FC DEVINFO_LEGACY Legacy Device Info 6.4.2 Register Description 6.4.2.1 DEVINFO_INFO - DI Information Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:24 DEVINFOREV...
  • Page 58 Reference Manual MSC - Memory System Controller 6.4.2.2 DEVINFO_PART - Part Info Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 29:24 FAMILY...
  • Page 59 Reference Manual MSC - Memory System Controller 6.4.2.3 DEVINFO_MEMINFO - Memory Info Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:16 DILEN Length of DI Page Length of DI area (number of 32-bit words included in CRC) 15:8 UDPAGESIZE User Data Page Size...
  • Page 60 Reference Manual MSC - Memory System Controller 6.4.2.5 DEVINFO_PKGINFO - Misc Device Info Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:16...
  • Page 61 Reference Manual MSC - Memory System Controller 6.4.2.6 DEVINFO_CUSTOMINFO - Custom Part Info Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 PARTNO Part Number Custom part identifier as unsigned integer (eg. 903). 65535 for standard product 15:0 Reserved To ensure compatibility with future devices, always write bits to 0.
  • Page 62 Reference Manual MSC - Memory System Controller 6.4.2.8 DEVINFO_SWCAPA0 - Software Restriction Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 21:20 RAIL Capability...
  • Page 63 Reference Manual MSC - Memory System Controller Name Reset Access Description 11:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RF4CE RF4CE Capability RF4CE stack capability level Value Mode Description LEVEL0 RF4CE stack capability not available LEVEL1...
  • Page 64 Reference Manual MSC - Memory System Controller 6.4.2.9 DEVINFO_SWCAPA1 - Software Restriction Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions GWEN Gateway...
  • Page 65 Reference Manual MSC - Memory System Controller 6.4.2.10 DEVINFO_EXTINFO - External Component Info Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:16...
  • Page 66 Reference Manual MSC - Memory System Controller 6.4.2.11 DEVINFO_EUI48L - EUI 48 Low Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:24 OUI48L OUI48L Lower Octet of EUI48 Organizationally Unique Identifier 23:0 UNIQUEID Unique ID Unique identifier 6.4.2.12 DEVINFO_EUI48H - EUI 48 High Offset Bit Position...
  • Page 67 Reference Manual MSC - Memory System Controller 6.4.2.13 DEVINFO_EUI64L - EUI64 Low Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:0 UNIQUEL UNIQUEL Lower 32 bits of EUI64 Unique Identifier 6.4.2.14 DEVINFO_EUI64H - EUI64 High Offset Bit Position 0x04C Reset Access...
  • Page 68 Reference Manual MSC - Memory System Controller 6.4.2.15 DEVINFO_CALTEMP - Calibration temperature Information Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TEMP...
  • Page 69 Reference Manual MSC - Memory System Controller 6.4.2.17 DEVINFO_HFRCODPLLCALn - HFRCODPLL Calibration Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:28 IREFTC Tempco Trim 27:26 CMPSEL Comparator Load Select 25:24 CLKDIV Locally Divide HFRCO Clock Output 23:21 CMPBIAS Comparator Bias Current 20:16...
  • Page 70 Reference Manual MSC - Memory System Controller 6.4.2.18 DEVINFO_HFRCOEM23CALn - HFRCOEM23 Calibration Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:28 IREFTC Tempco Trim 27:26 CMPSEL Comparator Load Select 25:24 CLKDIV Locally Divide HFRCO Clock Output 23:21 CMPBIAS Comparator Bias Current 20:16...
  • Page 71 Reference Manual MSC - Memory System Controller 6.4.2.19 DEVINFO_MODULENAME0 - Module Name Information Offset Bit Position 0x130 Reset Access Name Name Reset Access Description 31:24 MODCHAR4 0xFF Fourth character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR3 0xFF...
  • Page 72 Reference Manual MSC - Memory System Controller 6.4.2.21 DEVINFO_MODULENAME2 - Module Name Information Offset Bit Position 0x138 Reset Access Name Name Reset Access Description 31:24 MODCHAR12 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR11 0xFF...
  • Page 73 Reference Manual MSC - Memory System Controller 6.4.2.22 DEVINFO_MODULENAME3 - Module Name Information Offset Bit Position 0x13C Reset Access Name Name Reset Access Description 31:24 MODCHAR16 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR15 0xFF...
  • Page 74 Reference Manual MSC - Memory System Controller 6.4.2.23 DEVINFO_MODULENAME4 - Module Name Information Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:24 MODCHAR20 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR19 0xFF...
  • Page 75 Reference Manual MSC - Memory System Controller 6.4.2.24 DEVINFO_MODULENAME5 - Module Name Information Offset Bit Position 0x144 Reset Access Name Name Reset Access Description 31:24 MODCHAR24 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR23 0xFF...
  • Page 76 Reference Manual MSC - Memory System Controller 6.4.2.26 DEVINFO_MODULEINFO - Module Information Offset Bit Position 0x14C Reset Access Name Name Reset Access Description EXTVALID EXTINFO entry used Value Mode Description EXTUSED EXT used EXTUNUSED EXT not used PHYLIMITED PHY Limited Value Mode Description...
  • Page 77 Reference Manual MSC - Memory System Controller Name Reset Access Description LFXO Factory Calibrated Value Mode Description VALID LFXO Tuning in MODXOCAL is valid NOTVALID LFXO Tuning value in MODXOCAL is not valid EXPRESS Blue Gecko Express Value Mode Description SUPPORTED Blue Gecko Express is supported NONE...
  • Page 78 Reference Manual MSC - Memory System Controller 6.4.2.27 DEVINFO_MODXOCAL - Module External Oscillator Calibration Information Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 22:16...
  • Page 79 Reference Manual MSC - Memory System Controller 6.4.2.29 DEVINFO_IADC0GAIN1 - IADC Gain Calibration Offset Bit Position 0x184 Reset Access Name Name Reset Access Description 31:16 GAINCANA4 Input Gain = 4x 15:0 GAINCANA3 Input Gain = 3x 6.4.2.30 DEVINFO_IADC0OFFSETCAL0 - IADC Offset Calibration Offset Bit Position 0x188...
  • Page 80 Reference Manual MSC - Memory System Controller 6.4.2.31 DEVINFO_IADC0NORMALOFFSETCAL0 - IADC Offset Calibration Offset Bit Position 0x18C Reset Access Name Name Reset Access Description 31:16 OFFSETANA2NORM Normal mode offset gain adjustment term 15:0 OFFSETANA1NORM Normal mode analog offset term at OSR=2x, gain = 1x 6.4.2.32 DEVINFO_IADC0NORMALOFFSETCAL1 - IADC Offset Calibration Offset Bit Position...
  • Page 81 Reference Manual MSC - Memory System Controller 6.4.2.33 DEVINFO_IADC0HISPDOFFSETCAL0 - IADC Offset Calibration Offset Bit Position 0x194 Reset Access Name Name Reset Access Description 31:16 OFFSETANA2HISPD High speed mode offset gain adjustment term 15:0 OFFSETANA1HISPD High speed mode analog offset term at OSR=2x, gain = 1x 6.4.2.34 DEVINFO_IADC0HISPDOFFSETCAL1 - IADC Offset Calibration Offset Bit Position...
  • Page 82 Reference Manual MSC - Memory System Controller 6.4.2.35 DEVINFO_LEGACY - Legacy Device Info Offset Bit Position 0x1FC Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:16...
  • Page 83 Reference Manual MSC - Memory System Controller Name Reset Access Description EFR32BG13B EFR32 Blue Gecko Family Series 1 Device Config 3 EFR32BG13V EFR32 Blue Gecko Family Series 1 Device Config 3 EFR32FG13P EFR32 Flex Gecko Family Series 1 Device Config 3 EFR32FG13B EFR32 Flex Gecko Family Series 1 Device Config 3 EFR32FG13V...
  • Page 84: Icache - Instruction Cache

    Reference Manual MSC - Memory System Controller 6.5 ICACHE - Instruction Cache The ICACHE provides fast access to recently executed instructions improving both speed and power consumption of code execution. The instruction cache is enabled by default, but can be disabled by setting CACHEDIS in ICACHE_CTRL. When enabled, the instruc- tion cache typically reduces the number of flash reads significantly, thus saving energy.
  • Page 85: Performance Measurement

    Reference Manual MSC - Memory System Controller 6.5.2 Performance Measurement To measure the hit-rate of a code-section, the built-in performance counters can be used. Before the section, start the performance counters by setting STARTPC in ICACHE_CMD register. This starts the performance counters, counting from 0. At the end of the sec- tion, stop the performance counters by setting STOPPC in ICACHE_CMD.
  • Page 86: Register Map

    Reference Manual MSC - Memory System Controller 6.5.3 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ICACHE_IPVERSION IP Version 0x004 ICACHE_CTRL Control Register 0x008 ICACHE_PCHITS Performance Counter Hits 0x00C ICACHE_PCMISSES Performance Counter Misses 0x010 ICACHE_PCAHITS...
  • Page 87: Register Description

    Reference Manual MSC - Memory System Controller Offset Name Type Description 0x3014 ICACHE_STATUS_TGL Status Register 0x3018 ICACHE_CMD_TGL Command Register 0x301C ICACHE_LPMODE_TGL Low Power Mode 0x3020 ICACHE_IF_TGL RWH INTFLAG Interrupt Flag 0x3024 ICACHE_IEN_TGL Interrupt Enable 6.5.4 Register Description 6.5.4.1 ICACHE_IPVERSION - IP Version Offset Bit Position 0x000...
  • Page 88 Reference Manual MSC - Memory System Controller 6.5.4.2 ICACHE_CTRL - Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions AUTOFLUSHDIS Automatic Flushing Disable...
  • Page 89 Reference Manual MSC - Memory System Controller 6.5.4.4 ICACHE_PCMISSES - Performance Counter Misses Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:0 PCMISSES Performance Counter Misses Miss counter value 6.5.4.5 ICACHE_PCAHITS - Performance Counter Advanced Hits Offset Bit Position 0x010 Reset...
  • Page 90 Reference Manual MSC - Memory System Controller 6.5.4.6 ICACHE_STATUS - Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PCRUNNING PC Running...
  • Page 91 Reference Manual MSC - Memory System Controller 6.5.4.8 ICACHE_LPMODE - Low Power Mode Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions NESTFACTOR...
  • Page 92 Reference Manual MSC - Memory System Controller 6.5.4.9 ICACHE_IF - Interrupt Flag Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RAMERROR RAM error Interrupt Flag...
  • Page 93: Syscfg - System Configuration

    Reference Manual MSC - Memory System Controller 6.5.4.10 ICACHE_IEN - Interrupt Enable Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RAMERRORIEN RAM error Interrupt Enable...
  • Page 94: Ecc

    Reference Manual MSC - Memory System Controller 6.6.2 ECC DMEM0, FRCRAM, and SEQRAM support one bit correction and two bit detection ECC. To enable error detection for DMEM0, set RAMECCCHKEN in SYSCFG_DMEM0ECCCTRL. To enable error detection for FRCRAM and SEQRAM, set FRCRAMECCCHKEN and SEQRAMECCCHKEN in SYSCFG_RADIOECCCTRL.
  • Page 95: Register Map

    Reference Manual MSC - Memory System Controller 6.6.8 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 SYSCFG_IF RWH INTFLAG Interrupt Flag Register 0x004 SYSCFG_IEN Interrupt Enable Register 0x010 SYSCFG_CHIPREVHW Hardwired Chip Rev values 0x014 SYSCFG_CHIPREV Part Family and Revision values...
  • Page 96 Reference Manual MSC - Memory System Controller Offset Name Type Description 0x2004 SYSCFG_IEN_CLR Interrupt Enable Register 0x2010 SYSCFG_CHIPREVHW_CLR Hardwired Chip Rev values 0x2014 SYSCFG_CHIPREV_CLR Part Family and Revision values 0x2200 SYSCFG_CTRL_CLR Memory System Control Register 0x2208 SYSCFG_DMEM0RETNCTRL_C DMEM retention Control Register 0x2210 SYSCFG_DMEM0EC- DMEM ECC Error Address Register...
  • Page 97 Reference Manual MSC - Memory System Controller Offset Name Type Description 0x3414 SYSCFG_FRCRAMEC- FRCRAM ECC Error Address Register CADDR_TGL silabs.com | Building a more connected world. Rev. 0.4 | 97...
  • Page 98: Register Description

    Reference Manual MSC - Memory System Controller 6.6.9 Register Description 6.6.9.1 SYSCFG_IF - Interrupt Flag Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FRCRAMERR2BIF...
  • Page 99 Reference Manual MSC - Memory System Controller Name Reset Access Description Software Interrupt 0 Software interrupts silabs.com | Building a more connected world. Rev. 0.4 | 99...
  • Page 100 Reference Manual MSC - Memory System Controller 6.6.9.2 SYSCFG_IEN - Interrupt Enable Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FRCRAMERR2BIEN...
  • Page 101 Reference Manual MSC - Memory System Controller Name Reset Access Description Set to enable the Software Interrupts 6.6.9.3 SYSCFG_CHIPREVHW - Hardwired Chip Rev values Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:12...
  • Page 102 Reference Manual MSC - Memory System Controller 6.6.9.5 SYSCFG_CTRL - Memory System Control Register Offset Bit Position 0x200 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RAMECCERRFAULTEN 0x1...
  • Page 103 Reference Manual MSC - Memory System Controller 6.6.9.6 SYSCFG_DMEM0RETNCTRL - DMEM retention Control Register Offset Bit Position 0x208 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RAMRETNCTRL...
  • Page 104 Reference Manual MSC - Memory System Controller 6.6.9.7 SYSCFG_DMEM0ECCADDR - DMEM ECC Error Address Register Offset Bit Position 0x210 Reset Access Name Name Reset Access Description 31:0 DMEM0ECCADDR DMEM0 RAM ECC Error Address Indicates address of SysRAM banks at which ECC error occured 6.6.9.8 SYSCFG_DMEM0ECCCTRL - DMEM ECC Control Register Offset Bit Position...
  • Page 105 Reference Manual MSC - Memory System Controller 6.6.9.9 SYSCFG_DMEM0RAMCTRL - DMEM Control enable Register Offset Bit Position 0x218 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RAMPREFETCHEN...
  • Page 106 Reference Manual MSC - Memory System Controller 6.6.9.10 SYSCFG_RADIORAMRETNCTRL - RADIO RAM retention Control Register Offset Bit Position 0x400 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FRCRAMRETNCTRL...
  • Page 107 Reference Manual MSC - Memory System Controller 6.6.9.11 SYSCFG_RADIOECCCTRL - RADIO RAM ECC Control Register Offset Bit Position 0x408 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FRCRAMECCCHKEN...
  • Page 108 Reference Manual MSC - Memory System Controller 6.6.9.12 SYSCFG_RADIORAMCTRL - RADIO RAM Control Register Offset Bit Position 0x40C Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DEMODRAMCACHEEN 0x0...
  • Page 109 Reference Manual MSC - Memory System Controller 6.6.9.13 SYSCFG_SEQRAMECCADDR - SEQRAM ECC Error Address Register Offset Bit Position 0x410 Reset Access Name Name Reset Access Description 31:0 SEQRAMECCADDR SEQRAM ECC Error Address Indicates Address of SEQRAM at which ECC error occured 6.6.9.14 SYSCFG_FRCRAMECCADDR - FRCRAM ECC Error Address Register Offset Bit Position...
  • Page 110: Register Map

    Reference Manual MSC - Memory System Controller 6.7 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_IPVERSION IP version ID 0x008 MSC_READCTRL Read Control Register 0x00C MSC_WRITECTRL Write Control Register 0x010 MSC_WRITECMD Write Command Register...
  • Page 111 Reference Manual MSC - Memory System Controller Offset Name Type Description 0x11A0 MSC_TESTCTRL_SET Flash test control register 0x2000 MSC_IPVERSION_CLR IP version ID 0x2008 MSC_READCTRL_CLR Read Control Register 0x200C MSC_WRITECTRL_CLR Write Control Register 0x2010 MSC_WRITECMD_CLR Write Command Register 0x2014 MSC_ADDRB_CLR Page Erase/Write Address Buffer 0x2018 MSC_WDATA_CLR Write Data Register...
  • Page 112: Register Description

    Reference Manual MSC - Memory System Controller 6.8 Register Description 6.8.1 MSC_IPVERSION - IP version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 113: Msc_Readctrl - Read Control Register

    Reference Manual MSC - Memory System Controller 6.8.2 MSC_READCTRL - Read Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 21:20...
  • Page 114: Msc_Writectrl - Write Control Register

    Reference Manual MSC - Memory System Controller 6.8.3 MSC_WRITECTRL - Write Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions LPWRITE...
  • Page 115: Msc_Writecmd - Write Command Register

    Reference Manual MSC - Memory System Controller 6.8.4 MSC_WRITECMD - Write Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLEARWDATA...
  • Page 116: Msc_Addrb - Page Erase/Write Address Buffer

    Reference Manual MSC - Memory System Controller 6.8.5 MSC_ADDRB - Page Erase/Write Address Buffer Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:0 ADDRB Page Erase or Write Address Buffer This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_CMD is set.
  • Page 117: Msc_Status - Status Register

    Reference Manual MSC - Memory System Controller 6.8.7 MSC_STATUS - Status Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:28 PWRUPCKBDFAIL- Flash power up checkerboard pattern chec COUNT This field tells how many times checkboard pattern check fail occured after a reset sequence. WREADY Flash Write Ready When this bit is set, flash completes the power up sequence and ready for write/erase command.
  • Page 118: Msc_If - Interrupt Flag Register

    Reference Manual MSC - Memory System Controller Name Reset Access Description Set when software attempts to load an invalid (unmapped) address into ADDR LOCKED Access Locked When set, the last erase or write is aborted due to erase/write access constraints BUSY Erase/Write Busy When set, an erase or write operation is in progress and new commands are ignored...
  • Page 119: Msc_Ien - Interrupt Enable Register

    Reference Manual MSC - Memory System Controller 6.8.9 MSC_IEN - Interrupt Enable Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PWRUPF...
  • Page 120: Msc_Cmd - Command Register

    Reference Manual MSC - Memory System Controller 6.8.11 MSC_CMD - Command Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PWRUP Flash Power Up Command...
  • Page 121: Msc_Misclockword - Mass Erase And User Data Page Lock Word

    Reference Manual MSC - Memory System Controller 6.8.13 MSC_MISCLOCKWORD - Mass erase and User data page lock word Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions UDLOCKBIT...
  • Page 122: Msc_Pagelock1 - Main Space Page 32-63 Lock Word

    Reference Manual MSC - Memory System Controller 6.8.15 MSC_PAGELOCK1 - Main space page 32-63 lock word Offset Bit Position 0x124 Reset Access Name Name Reset Access Description 31:0 LOCKBIT page lock bit Zero means the corresponding page can be written/erased. Setting a bit will prevent corresponding page from being modified.
  • Page 123: Msc_Pagelock3 - Main Space Page 96-127 Lock Word

    Reference Manual MSC - Memory System Controller 6.8.17 MSC_PAGELOCK3 - Main space page 96-127 lock word Offset Bit Position 0x12C Reset Access Name Name Reset Access Description 31:0 LOCKBIT page lock bit Zero means the corresponding page can be written/erased. Setting a bit will prevent corresponding page from being modified.
  • Page 124: Dbg - Debug Interface

    Reference Manual DBG - Debug Interface 7. DBG - Debug Interface Quick Facts What? The Debug Interface is used to program and debug EFR32xG21 devices. Why? The Debug Interface makes it easy to re-program and update the system in the field, and allows de- bugging with minimal I/O pin usage.
  • Page 125: Functional Description

    Reference Manual DBG - Debug Interface 7.3 Functional Description There are three debug pins and four trace pins available on the device. Operation of these pins are described in the following section. 7.3.1 Debug Pins The following pins are the debug connections for the device: •...
  • Page 126: Register Map

    Reference Manual DBG - Debug Interface 7.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x1000 DBG_DCIWDATA Write Data 0x1004 DBG_DCIRDATA Read Data 0x1008 DBG_DCISTATUS Status 0x10FC DBG_DCIID Identification 0x1110 DBG_SYSCOM0 Communication Status 0x1114 DBG_SYSCOM1...
  • Page 127: Dbg_Dcistatus - Status

    Reference Manual DBG - Debug Interface 7.5.3 DBG_DCISTATUS - Status Offset Bit Position 0x1008 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RDATAVALID Read Data Valid Response from the challenge interface is valid.
  • Page 128: Dbg_Syscom0 - Communication Status

    Reference Manual DBG - Debug Interface 7.5.5 DBG_SYSCOM0 - Communication Status Offset Bit Position 0x1110 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RADIOSYNTHEN RADIO Synthesizer Enabled...
  • Page 129: Dbg_Syscom1 - Communication Status

    Reference Manual DBG - Debug Interface 7.5.6 DBG_SYSCOM1 - Communication Status Offset Bit Position 0x1114 Reset Access Name Name Reset Access Description 31:20 Peripheral Reflex Signals Peripheral Reflex Signal Channel Value 19:0 GPIO General Purpose Input General Purpose Input Value silabs.com | Building a more connected world.
  • Page 130: Dbg_Syspwr0 - Power Status

    Reference Manual DBG - Debug Interface 7.5.7 DBG_SYSPWR0 - Power Status Offset Bit Position 0x1120 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RTNDRAM5 Retained RAM5...
  • Page 131 Reference Manual DBG - Debug Interface Name Reset Access Description Energy Mode 0 System is in Energy Mode 0 silabs.com | Building a more connected world. Rev. 0.4 | 131...
  • Page 132: Dbg_Sysclk0 - Clocking Status

    Reference Manual DBG - Debug Interface 7.5.8 DBG_SYSCLK0 - Clocking Status Offset Bit Position 0x1130 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RNGULFRCO Running ULFRCO Clock...
  • Page 133 Reference Manual DBG - Debug Interface Name Reset Access Description ACMP1 Clock is running RNGACMP0 Running ACMP0 Clock ACMP0 Clock is running RNGIADC Running IADC Clock IADC Clock is running RNGDPLL Running DPLL Clock DPLL Clock is running RNGLDMA Running LDMA Clock LDMA Clock is running RNGGPCRC Running GPCRC Clock...
  • Page 134: Dbg_Sysid - Identification

    Reference Manual DBG - Debug Interface 7.5.9 DBG_SYSID - Identification Offset Bit Position 0x11FC Reset Access Name Name Reset Access Description 31:0 0x5451D Identification System Block ID silabs.com | Building a more connected world. Rev. 0.4 | 134...
  • Page 135: Cmu - Clock Management Unit

    Reference Manual CMU - Clock Management Unit 8. CMU - Clock Management Unit Quick Facts WDOG clock What? The CMU controls clock switching and distribution. LETIMER clock EFR32xG21 supports 7 different oscillators with minimized power consumption and short start-up RTCC clock time.
  • Page 136: Functional Description

    Reference Manual CMU - Clock Management Unit 8.3 Functional Description An overview of the CMU is shown in Figure 8.1 CMU Overview on page 137. This figure shows the CMU for the largest device in the EFR32xG21 family. Please refer to the Configuration Summary in the Device Datasheet to see which core and peripheral modules, and therefore clock connections, are present in a specific device.
  • Page 137 Reference Manual CMU - Clock Management Unit HFXO HCLKRADIO branch Radio gate CMU_RADIOCLKCTRL. (hidden) LSPCLK prescaler I2C0 /1, /2 CMU_SYSCLKCTRL. LSPCLKPRESC FSRCO PCLK USARTn prescaler /1, /2 I2C1 (FSRCO) CMU_SYSCLKCTRL. HFXO PCLKPRESC HFXO HFRCODPLL clock switch CLKIN0 SYSCLK HCLK LDMA GPCRC prescaler /1, /2, /4...
  • Page 138: System Clocks

    Reference Manual CMU - Clock Management Unit Note: This figure does not necessarilly show every clock for every peripheral. These are documented in the register descriptions. 8.3.1 System Clocks 8.3.1.1 SYSCLK - Bus Clock SYSCLK is the selected System Clock. HCLK is an optionally prescaled version of SYSCLK. PCLK is an optionally prescaled version of HCLK.
  • Page 139 Reference Manual CMU - Clock Management Unit 8.3.1.6 EM01GRPACLK - Energy Mode 01 Group A Clock EM01GRPACLK is the selected clock for the Group A Peripherals operating in Energy Modes 0 or 1. These are typically high clock frequency peripheral modules. There are four selectable sources for EM01GRPACLK: HFXO, HFRCODPLL, HFRCOEM23, and FSRCO.
  • Page 140: Switching Clock Source

    Reference Manual CMU - Clock Management Unit 8.3.2 Switching Clock Source The FSRCO oscillator is a fixed frequency (20 MHz), low energy oscillator with extremely short start-up time. Therefore, this oscillator is chosen by hardware as the clock source for SYSCLK when the device starts up (e.g. after reset). Software can switch between the different clock sources at run-time.
  • Page 141 Reference Manual CMU - Clock Management Unit CMU_SYSCLKCTRL.CLKSEL HFRCO_CTRL.FORCEEN HFRCO_CTRL.DISONDEMAND HFXO_CTRL.FORCEEN HFXO_CTRL.DISONDEMAND HFRCO_STATUS.RDY HFRCO_STATUS.ENS HFXO_STATUS.RDY HFXO_STATUS.ENS BUSCLK HFRCO HFXO HFXO time-out period Figure 8.3. CMU Switching from HFRCO to HFXO after HFXO is ready Switching clock source for various clock switches is done by setting the CLKSEL bitfields in CMU_*CLKCTRL. To ensure no stalls in the peripherals, the clock source should be ready before switching to it.
  • Page 142: Rc Oscillator Calibration

    Reference Manual CMU - Clock Management Unit 8.3.3 RC Oscillator Calibration The CMU has built-in HW support to efficiently calibrate the RC oscillators (LFRCO, HFRCODPLL, HFRCOEM23) at run-time, see Figure 8.4 HW-support for RC Oscillator Calibration on page 142 for an illustration of this circuit. The concept is to select a reference and compare the RC frequency with the reference frequency.
  • Page 143 Reference Manual CMU - Clock Management Unit Up-counter sampled and CALRDY interrupt flag set. Sampled value available in CMU_CALCNT. Up-counter CALTOP Down-counter Calibration Started Calibration Stopped (counters stopped) Figure 8.5. Single Calibration (CONT=0) silabs.com | Building a more connected world. Rev.
  • Page 144 Reference Manual CMU - Clock Management Unit Up-counter sampled and CALRDY interrupt Up-counter sampled and CALRDY interrupt flag set. flag set. Sampled value available in CMU_CALCNT. Sampled value available in CMU_CALCNT. Up-counter CALTOP Down-counter Calibration Started Figure 8.6. Continuous Calibration (CONT=1) silabs.com | Building a more connected world.
  • Page 145: Energy Modes

    Reference Manual CMU - Clock Management Unit 8.3.4 Energy Modes The availability of oscillators and system clocks depends on the chosen energy mode. By default, the high frequency oscillators (HFRCODPLL, HFRCOEM23, and HFXO) and high frequency clocks (SYSCLK, HCLK, PCLK, RADIOCLK, and EM01GRPACLK) are available down to EM1 Sleep.
  • Page 146: Clock Input From A Pin

    Reference Manual CMU - Clock Management Unit 8.3.6 Clock Input from a Pin It is possible to configure the CMU to input a clock from the CMU_CLKI0. This clock can be selected to drive SYSCLK and DPLL refer- ence using CMU_SYSCLKCTRL.CLKSEL and CMU_DPLLREFCLKCTRL.CLKSEL respectively. The required input pin locations can be configured in the GPIO_DBUSCMU_CLKIN0ROUTE register.
  • Page 147: Register Map

    Reference Manual CMU - Clock Management Unit 8.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_IPVERSION IP version ID 0x008 CMU_STATUS Status Register 0x010 CMU_LOCK Configuration Lock Register 0x014 CMU_WDOGLOCK WDOG Configuration Lock Register 0x020...
  • Page 148 Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x1120 CMU_EM01GRPACLKCTRL_SE EM01 Peripheral Group A Clock Control 0x1140 CMU_EM23GRPACLKCTRL_SE EM23 Peripheral Group A Clock Control 0x1160 CMU_EM4GRPACLKCTRL_SET EM4 Peripheral Group A Clock Control 0x1180 CMU_IADCCLKCTRL_SET IADC Clock Control 0x1200 CMU_WDOG0CLKCTRL_SET Watchdog0 Clock Control...
  • Page 149: Register Description

    Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x3050 CMU_CALCMD_TGL Calibration Command Register 0x3054 CMU_CALCTRL_TGL Calibration Control Register 0x3058 CMU_CALCNT_TGL Calibration Result Counter Register 0x3070 CMU_SYSCLKCTRL_TGL System Clock Control 0x3080 CMU_TRACECLKCTRL_TGL Debug Trace Clock Control 0x3090 CMU_EXPORTCLKCTRL_TGL Export Clock Control 0x3100 CMU_DPLLREFCLKCTRL_TGL...
  • Page 150: Cmu_Status - Status Register

    Reference Manual CMU - Clock Management Unit 8.5.2 CMU_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description LOCK Configuration Lock Status Indicates the current status of configuration lock Value Mode Description UNLOCKED LOCKED WDOGLOCK Configuration Lock Status for WDOG Indicates the current status of WDOG configuration lock Value...
  • Page 151: Cmu_Lock - Configuration Lock Register

    Reference Manual CMU - Clock Management Unit 8.5.3 CMU_LOCK - Configuration Lock Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0...
  • Page 152: Cmu_Ien - Interrupt Enable Register

    Reference Manual CMU - Clock Management Unit 8.5.5 CMU_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CALOF...
  • Page 153: Cmu_Calcmd - Calibration Command Register

    Reference Manual CMU - Clock Management Unit 8.5.7 CMU_CALCMD - Calibration Command Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CALSTOP...
  • Page 154: Cmu_Calctrl - Calibration Control Register

    Reference Manual CMU - Clock Management Unit 8.5.8 CMU_CALCTRL - Calibration Control Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:28 DOWNSEL Calibration Down-counter Select Selects clock source for the calibration down-counter. Only change when calibration circuit is off. Value Mode Description...
  • Page 155: Cmu_Calcnt - Calibration Result Counter Register

    Reference Manual CMU - Clock Management Unit Name Reset Access Description Set this bit to enable continuous calibration 22:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:0 CALTOP Calibration Counter Top Value Write top value before calibration.
  • Page 156: Cmu_Sysclkctrl - System Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.10 CMU_SYSCLKCTRL - System Clock Control Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 13:12...
  • Page 157: Cmu_Traceclkctrl - Debug Trace Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.11 CMU_TRACECLKCTRL - Debug Trace Clock Control Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLKSEL...
  • Page 158: Cmu_Exportclkctrl - Export Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.12 CMU_EXPORTCLKCTRL - Export Clock Control Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 28:24...
  • Page 159 Reference Manual CMU - Clock Management Unit Name Reset Access Description ULFRCO ULFRCO is clocking CLKOUT1 LFRCO LFRCO is clocking CLKOUT1 LFXO LFXO is clocking CLKOUT1 HFRCODPLL HFRCODPLL is clocking CLKOUT1 HFRCOEM23 HFRCOEM23 is clocking CLKOUT1 HFXO HFXO is clocking CLKOUT1 FSRCO FSRCO is clocking CLKOUT1 Reserved...
  • Page 160: Cmu_Dpllrefclkctrl - Digital Pll Reference Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.13 CMU_DPLLREFCLKCTRL - Digital PLL Reference Clock Control Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLKSEL...
  • Page 161: Cmu_Em01Grpaclkctrl - Em01 Peripheral Group A Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.14 CMU_EM01GRPACLKCTRL - EM01 Peripheral Group A Clock Control Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLKSEL...
  • Page 162: Cmu_Em4Grpaclkctrl - Em4 Peripheral Group A Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.16 CMU_EM4GRPACLKCTRL - EM4 Peripheral Group A Clock Control Offset Bit Position 0x160 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLKSEL...
  • Page 163: Cmu_Wdog0Clkctrl - Watchdog0 Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.18 CMU_WDOG0CLKCTRL - Watchdog0 Clock Control Offset Bit Position 0x200 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLKSEL...
  • Page 164: Cmu_Wdog1Clkctrl - Watchdog1 Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.19 CMU_WDOG1CLKCTRL - Watchdog1 Clock Control Offset Bit Position 0x208 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLKSEL...
  • Page 165: Cmu_Radioclkctrl - Radio Clock Control

    Reference Manual CMU - Clock Management Unit 8.5.21 CMU_RADIOCLKCTRL - Radio Clock Control Offset Bit Position 0x280 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Enable...
  • Page 166: Oscillators

    Reference Manual Oscillators 9. Oscillators Quick Facts What? The EFR32xG21 has a wide range of high frequency and low frequency oscillators. Why? The High Frequency oscillators support EM0/1 oper- ation. The Low-frequency oscillators provide a low frequency clock for the low energy peripherals in EM/2/3/4.
  • Page 167: Functional Description

    Reference Manual Oscillators 9.2.3 Functional Description 9.2.3.1 Enabling and Disabling While the HFXO supports on-demand clocking, it is generally recommended to manually manage the HFXO, at least initially, because it requires software configuration and has a long start-up time. Software can set the FORCEEN to start HFXO and keep it enabled even if it is not selected as a clock source.
  • Page 168 Reference Manual Oscillators 9.2.3.3 Configuration The High Frequency Crystal Oscillator needs to be configured to ensure safe start-up for the given crystal. Refer to the Device Data sheet and application notes for guidelines in selecting correct components and crystals as well as for configuration trade-offs. The HFXO crystal is connected to the HFXTAL_I/HFXTAL_O pins as shown in Figure 9.1 HFXO Pin Connection on page 168.
  • Page 169 Reference Manual Oscillators 9.2.3.5 On-Demand Clocking Enabling the HFXO can be requested by hardware. On-demand HFXO enable can be used, for example, upon wake-up of the Radio Controller (RAC). The RAC module always requires the HFXO for its operation. Any hardware request for HFXO, including request from RAC, is indicated in the HWREQ bit field of the HFXO_STATUS register.
  • Page 170: Register Map

    Reference Manual Oscillators 9.2.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 HFXO_IPVERSION IP version ID 0x010 HFXO_XTALCFG Crystal Configuration Register 0x018 HFXO_XTALCTRL Crystal Control Register 0x020 HFXO_CFG Configuration Register 0x028 HFXO_CTRL Control Register...
  • Page 171: Register Description

    Reference Manual Oscillators Offset Name Type Description 0x3050 HFXO_CMD_TGL Command Register 0x3058 HFXO_STATUS_TGL Status Register 0x3070 HFXO_IF_TGL RWH INTFLAG Interrupt Flag Register 0x3074 HFXO_IEN_TGL Interrupt Enable Register 0x3080 HFXO_LOCK_TGL Configuration Lock Register 9.2.5 Register Description 9.2.5.1 HFXO_IPVERSION - IP version ID Offset Bit Position 0x000...
  • Page 172 Reference Manual Oscillators 9.2.5.2 HFXO_XTALCFG - Crystal Configuration Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:24 TIMEOUTCBLSB Core Bias LSB Change Timeout wait duration for the COREBIAS change to settle out, used at each step of COREBIAS optimization algorithm...
  • Page 173 Reference Manual Oscillators Name Reset Access Description T16US T41US T83US T125US T166US T208US T250US T333US T416US T500US T666US T833US T1666US T2500US T4166US T7500US 19:16 CTUNEXOSTARTUP Startup Tuning Capacitance on XO 4 most significant bits of CTUNEXOANA applied during startup phase 15:12 CTUNEXISTARTUP Startup Tuning Capacitance on XI...
  • Page 174 Reference Manual Oscillators 9.2.5.3 HFXO_XTALCTRL - Crystal Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description SKIPCOREBIASOPT Skip Core Bias Optimization Set to skip the core bias current optimization algorithm at next startup. Reuse the value stored in COREBIASANA. At the successful completion of core bias current optimization algorithm, hardware sets this bit to skip optimization during sub- sequent startup.
  • Page 175 Reference Manual Oscillators Name Reset Access Description Approximately 10uA per step 9.2.5.4 HFXO_CFG - Configuration Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SQBUFSCHTRGANA...
  • Page 176 Reference Manual Oscillators 9.2.5.5 HFXO_CTRL - Control Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FORCEXO2GNDANA Force XO Pin to Ground Set to enable grounding of XO pin.
  • Page 177 Reference Manual Oscillators 9.2.5.6 HFXO_CMD - Command Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions COREBIASOPT Core Bias Optimizaton Starts the core bias current optimization algorithm and runs it one time.
  • Page 178 Reference Manual Oscillators 9.2.5.7 HFXO_STATUS - Status Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description LOCK Configuration Lock Status Indicates the current status of configuration lock Value Mode Description UNLOCKED LOCKED FSMLOCK FSM Lock Status Indicates the current status of configuration locked by FSM running Value Mode Description...
  • Page 179 Reference Manual Oscillators 9.2.5.8 HFXO_IF - Interrupt Flag Register Offset Bit Position 0x070 Reset Access Name Name Reset Access Description COREBIASOPTERR Core Bias Optimization Error Interrupt Core bias current optimization algorithm fails to complete. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DNSERR...
  • Page 180 Reference Manual Oscillators 9.2.5.9 HFXO_IEN - Interrupt Enable Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description COREBIASOPTERR Core Bias Optimization Error Interrupt Core bias current optimization algorithm fails to complete. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DNSERR...
  • Page 181: Hfrco - High-Frequency Rc Oscillator

    Reference Manual Oscillators 9.2.5.10 HFXO_LOCK - Configuration Lock Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0 LOCKKEY 0x580E Configuration Lock Key...
  • Page 182 Reference Manual Oscillators 9.3.3.3 Calibration Several different frequencies are calibrated during production test on every device. In order to use a factory-calibrated value, software must read the value from the appropriate location in the DEVINFO page and write it to the CAL register. TUNING and FINETUNING in CAL register can be used to trim HFRCO manually.
  • Page 183 Reference Manual Oscillators 9.3.3.5 Status Flags 9.3.3.5.1 FREQBSY The FREQBSY bit indicates HFRCO is busy updating frequency after writing to the CAL register. The FREQBSY bit should be used whenever frequency is changed. E.g. After software writes to the CAL register, FREQBSY would assert immediately. Software should wait for FREQBSY to be zero before attempting to write to the CAL register again.
  • Page 184: Register Map

    Reference Manual Oscillators 9.3.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 HFRCO_IPVERSION IP Version ID 0x004 HFRCO_CTRL Ctrl Register 0x008 HFRCO_CAL RWH SYNC Calibration Register 0x00C HFRCO_STATUS Status Register 0x010 HFRCO_IF RWH INTFLAG...
  • Page 185: Register Description

    Reference Manual Oscillators 9.3.5 Register Description 9.3.5.1 HFRCO_IPVERSION - IP Version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 186 Reference Manual Oscillators 9.3.5.3 HFRCO_CAL - Calibration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 IREFTC Tempco Trim on Comparator Current Writing this field adjusts the temperature coefficient trim on comparator current. 27:26 CMPSEL Comparator Load Select Writing this field adjusts the active load for comparators.
  • Page 187 Reference Manual Oscillators 9.3.5.4 HFRCO_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description LOCK Lock Status If set, all HFRCO lockable registers are locked. Value Mode Description UNLOCKED LOCKED 30:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Enable Status...
  • Page 188 Reference Manual Oscillators 9.3.5.5 HFRCO_IF - Interrupt Flag Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Ready Interrupt Flag Set when HFRCO is ready (start-up time exceeded).
  • Page 189: Dpll - Digital Phased Locked Loop

    Reference Manual Oscillators 9.3.5.7 HFRCO_LOCK - Lock Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0 LOCKKEY 0x8195 Lock Key Write any other value than the unlock code to lock registers from editing.
  • Page 190 Reference Manual Oscillators 9.4.3.1 Enabling and Disabling The DPLL can be enabled and disabled by software via the DPLL_EN register. Before enabling DPLL, software should: 1. Select reference clock by setting the CLKSEL field in CMU_DPLLREFCLKCTRL; 2. The CMU should not be running from the HFRCO. If necessary, the CMU should switch to the FSRCO until after the DPLL has locked to avoid over-clocking due to overshoot.
  • Page 191: Register Map

    Reference Manual Oscillators 9.4.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DPLL_IPVERSION New Register 0x004 DPLL_EN RW ENABLE New Register 0x008 DPLL_CFG RW CONFIG New Register 0x00C DPLL_CFG1 RW CONFIG New Register 0x010 DPLL_IF...
  • Page 192: Register Description

    Reference Manual Oscillators 9.4.5 Register Description 9.4.5.1 DPLL_IPVERSION - New Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 193 Reference Manual Oscillators 9.4.5.3 DPLL_CFG - New Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DITHEN Dither Enable Control Set to enable dither function Reserved To ensure compatibility with future devices, always write bits to 0.
  • Page 194 Reference Manual Oscillators 9.4.5.4 DPLL_CFG1 - New Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:16 Factor N The locked DCO frequency is given by: Fdco = Fref * (N + 1)/(M+1).
  • Page 195 Reference Manual Oscillators 9.4.5.6 DPLL_IEN - New Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable LOCKFAILLOW LOCKFAILLOW Interrupe Enable LOCK...
  • Page 196 Reference Manual Oscillators 9.4.5.7 DPLL_STATUS - New Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description LOCK Lock Status Indicates the current status of configuration lock Value Mode Description UNLOCKED LOCKED 30:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Enable Status...
  • Page 197: Lfxo - Low-Frequency Crystal Oscillator

    Reference Manual Oscillators 9.5 LFXO - Low-Frequency Crystal Oscillator 9.5.1 Introduction The Low Frequency Crystal Oscillator (LFXO) uses an external 32.768 kHz crystal to provide an accurate low-frequency clock. The module is available in all energy modes, except EM3. The main interaction is with the CMU through the clock requesting mechanism. 9.5.2 Features High-level features.
  • Page 198 Reference Manual Oscillators 9.5.3.4 Edge Detection Interrupts There is a possibility for software to detect rising or falling edges of LFXO clock. The edge detection is enabled if any of POSEDGEIEN and NEGEDGEIEN is set to 1. The corresponding flags are available in POSEDGEIF and NEGEDGEIF. If none of the interrupts are enabled, the edge detection is disabled and POSEDGEIF and NEGEDGEIF hold their last value until cleared or set by software.
  • Page 199: Register Map

    Reference Manual Oscillators 9.5.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LFXO_IPVERSION LFXO IP version 0x004 LFXO_CTRL LFXO Control Register 0x008 LFXO_CFG LFXO Configuration Register 0x010 LFXO_STATUS LFXO Status Register 0x014 LFXO_CAL RW LFSYNC...
  • Page 200: Register Description

    Reference Manual Oscillators Offset Name Type Description 0x3024 LFXO_LOCK_TGL Configuration Lock Register 9.5.5 Register Description 9.5.5.1 LFXO_IPVERSION - LFXO IP version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 201 Reference Manual Oscillators 9.5.5.2 LFXO_CTRL - LFXO Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable Set this bit to enable EM4 exit on the oscillator failure detection.
  • Page 202 Reference Manual Oscillators 9.5.5.3 LFXO_CFG - LFXO Configuration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 10:8 TIMEOUT LFXO Start-up Delay Configures the start-up delay for LFXO.
  • Page 203 Reference Manual Oscillators Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions HIGHAMPL LFXO High Amplitude Enable Set this bit to enable high XTAL oscillation amplitude. LFXO AGC Enable Set this bit to enable automatic gain control which limits XTAL oscillation amplitude.
  • Page 204 Reference Manual Oscillators 9.5.5.5 LFXO_CAL - LFXO Calibration Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions GAIN LFXO Startup Gain The optimal value depends on the chosen crystal.
  • Page 205 Reference Manual Oscillators 9.5.5.6 LFXO_IF - Interrupt Flag Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FAIL LFXO Failure Interrupt Flag Set when LFXO failure is detected.
  • Page 206 Reference Manual Oscillators 9.5.5.7 LFXO_IEN - Interrupt Enable Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FAIL LFXO Failure Interrupt Enable Write 1 to enable FAILIF NEGEDGE...
  • Page 207: Lfrco - Low-Frequency Rc Oscillator

    Reference Manual Oscillators 9.5.5.9 LFXO_LOCK - Configuration Lock Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0 LOCKKEY 0x1A20 Lock Key...
  • Page 208 Reference Manual Oscillators 9.6.3.2 On-Demand Clocking All oscillators are part of an on-demand architecture. This means that LFRCO receives a request for clock from the CMU whenever the oscillator clock is needed. These requests can come at any time from any peripheral in any power domain. (Please see the chap- ter for additional information about on-demand clock generation.) 9.6.3.3 Calibration...
  • Page 209: Register Map

    Reference Manual Oscillators 9.6.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LFRCO_IPVERSION IP version 0x008 LFRCO_STATUS Status Register 0x00C LFRCO_CAL Calibration Register 0x014 LFRCO_IF RWH INTFLAG Interrupt Flag Register 0x018 LFRCO_IEN Interrupt Enable Register...
  • Page 210: Register Description

    Reference Manual Oscillators 9.6.5 Register Description 9.6.5.1 LFRCO_IPVERSION - IP version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 211 Reference Manual Oscillators 9.6.5.3 LFRCO_CAL - Calibration Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FREQTRIM 0xA5 Frequency Trim Trims the clock frequency of the LFRCO 9.6.5.4 LFRCO_IF - Interrupt Flag Register...
  • Page 212 Reference Manual Oscillators 9.6.5.5 LFRCO_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions NEGEDGE Falling Edge Interrupt Enable Enables the negedge interrupt and will cause the oscillator to run.
  • Page 213: Fsrco - Fast Start Rco

    Reference Manual Oscillators 9.6.5.7 LFRCO_LOCK - Configuration Lock Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0 LOCKKEY 0x2603 Lock Key...
  • Page 214: Register Description

    Reference Manual Oscillators 9.7.5 Register Description 9.7.5.1 FSRCO_IPVERSION - IP Version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 215: Smu - Security Management Unit

    Reference Manual SMU - Security Management Unit 10. SMU - Security Management Unit Quick Facts What? The Security Management Unit (SMU) provides con- figuration and status reporting for ARM TrustZone on the EFR32xG21. Why? Enables a robust solution at the system level. How? Hardware context switching and enhanced security provided by ARM Trust Zone.
  • Page 216: Functional Description

    Reference Manual SMU - Security Management Unit 10.3 Functional Description 10.3.1 Bus Level Security Bus level security is the ability to control the flow of information on the device. The components of bus level security are the Cortex- M33, the BMPU, and the PPU as highlighted in Figure 10.1 Bus Level Security Implementation on page 216.
  • Page 217: Privileged Access Control

    Reference Manual SMU - Security Management Unit 10.3.2 Privileged Access Control The Cortex-M33 and all other masters can be in either the privileged or unprivileged state. All bus access to peripherals are tested for privilege level by the PPU and resolved as shown in Table 10.1 Privileged Access Table on page 217.
  • Page 218: Arm Trust Zone

    Reference Manual SMU - Security Management Unit 10.3.4 ARM Trust Zone ARM Trust Zone is used to control what addresses are accessible by the CPU at any given time. There are two security states: secure and non-secure. In addition the MPU provides two privilege levels: privileged and unprivileged. This results in 4 possible states: secure- privileged, non-secure-privileged, secure-unprivileged and non-secure-unprivileged.
  • Page 219: Configuring Memory

    Reference Manual SMU - Security Management Unit 10.3.7 Configuring Memory The SMU provides the ability to configure the security attribute of memory. There are 8 configurable regions in total. There are three regions in FLASH (0 - 2) and three in RAM (4-6) which have pre-determined secure attributes and user selectable sizes. The final re- gions (3, 8) cover the flash info page and ARM EPPB space respectively and have a fixed size.
  • Page 220: Exception Handling

    Reference Manual SMU - Security Management Unit 10.3.9 Exception Handling When a BMPU detects a non-secure master attempting to access a secure address, the BMPUSECIF in SMU_IF is set and the ID of the Master block written to SMU_BMPUFS. If BMPUSECIEN is set and the SMU's Secure IRQ enabled, the CPU will be interrupted. When a PPU detects an access to a secure peripheral at its non-secure address or an access to a non-secure peripheral at its secure address, PPUSECIF in SMU_IF is set and the ID of the peripheral being accessed written to SMU_PPUFS.
  • Page 221: Register Map

    Reference Manual SMU - Security Management Unit 10.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 SMU_IPVERSION IP Version 0x004 SMU_STATUS Status Register 0x008 SMU_LOCK Lock Register 0x00C SMU_IF RWH INTFLAG Interrupt Flag Register 0x010 SMU_IEN...
  • Page 222 Reference Manual SMU - Security Management Unit Offset Name Type Description 0x1254 SMU_BMPUFSADDR_SET Fault Status Address 0x1260 SMU_ESAURTYPES0_SET Region Types 0 0x1264 SMU_ESAURTYPES1_SET Region Types 1 0x1270 SMU_ESAUMRB01_SET Movable Region Boundary 0x1274 SMU_ESAUMRB12_SET Movable Region Boundary 0x1280 SMU_ESAUMRB45_SET Movable Region Boundary 0x1284 SMU_ESAUMRB56_SET Movable Region Boundary...
  • Page 223: Register Description

    Reference Manual SMU - Security Management Unit Offset Name Type Description 0x3064 SMU_PPUSATD1_TGL Secure Access 0x3140 SMU_PPUFS_TGL Fault Status 0x3150 SMU_BMPUPATD0_TGL Privileged Attribute 0x3170 SMU_BMPUSATD0_TGL Secure Attribute 0x3250 SMU_BMPUFS_TGL Fault Status 0x3254 SMU_BMPUFSADDR_TGL Fault Status Address 0x3260 SMU_ESAURTYPES0_TGL Region Types 0 0x3264 SMU_ESAURTYPES1_TGL Region Types 1...
  • Page 224: Smu_Status - Status Register

    Reference Manual SMU - Security Management Unit 10.5.2 SMU_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SMUPRGERR SMU Programming Error...
  • Page 225: Smu_If - Interrupt Flag Register

    Reference Manual SMU - Security Management Unit 10.5.4 SMU_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions BMPUSEC...
  • Page 226: Smu_Ien - Interrupt Enable Register

    Reference Manual SMU - Security Management Unit 10.5.5 SMU_IEN - Interrupt Enable Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions BMPUSEC...
  • Page 227: Smu_M33Ctrl - M33 Control Settings

    Reference Manual SMU - Security Management Unit 10.5.6 SMU_M33CTRL - M33 Control Settings Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions LOCKSAU...
  • Page 228: Smu_Ppupatd0 - Privileged Access

    Reference Manual SMU - Security Management Unit 10.5.7 SMU_PPUPATD0 - Privileged Access Offset Bit Position 0x040 Reset Access Name Name Reset Access Description RTCC RTCC Privileged Access RTCC Privileged Access GPCRC GPCRC Privileged Access GPCRC Privileged Access IFADCDEBUG IFADCDEBUG Privileged Access IFADCDEBUG Privileged Access BURAM BURAM Privileged Access...
  • Page 229 Reference Manual SMU - Security Management Unit Name Reset Access Description TIMER2 Privileged Access TIMER1 TIMER1 Privileged Access TIMER1 Privileged Access TIMER0 TIMER0 Privileged Access TIMER0 Privileged Access LDMAXBAR LDMAXBAR Privileged Access LDMAXBAR Privileged Access LDMA LDMA Privileged Access LDMA Privileged Access GPIO GPIO Privileged Access GPIO Privileged Access...
  • Page 230: Smu_Ppupatd1 - Privileged Access

    Reference Manual SMU - Security Management Unit 10.5.8 SMU_PPUPATD1 - Privileged Access Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SEMAILBOX SE MAILBOX Privileged Access...
  • Page 231 Reference Manual SMU - Security Management Unit Name Reset Access Description LETIMER0 LETIMER0 Privileged Access LETIMER0 Privileged Access silabs.com | Building a more connected world. Rev. 0.4 | 231...
  • Page 232: Smu_Ppusatd0 - Secure Access

    Reference Manual SMU - Security Management Unit 10.5.9 SMU_PPUSATD0 - Secure Access Offset Bit Position 0x060 Reset Access Name Name Reset Access Description RTCC RTCC Secure Access RTCC Secure Access GPCRC GPCRC Secure Access GPCRC Secure Access IFADCDEBUG IFADCDEBUG Secure Access IFADCDEBUG Secure Access BURAM BURAM Secure Access...
  • Page 233 Reference Manual SMU - Security Management Unit Name Reset Access Description TIMER2 Secure Access TIMER1 TIMER1 Secure Access TIMER1 Secure Access TIMER0 TIMER0 Secure Access TIMER0 Secure Access LDMAXBAR LDMAXBAR Secure Access LDMAXBAR Secure Access LDMA LDMA Secure Access LDMA Secure Access GPIO GPIO Secure Access GPIO Secure Access...
  • Page 234: Smu_Ppusatd1 - Secure Access

    Reference Manual SMU - Security Management Unit 10.5.10 SMU_PPUSATD1 - Secure Access Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SEMAILBOX SE MAILBOX Secure Access...
  • Page 235: Smu_Ppufs - Fault Status

    Reference Manual SMU - Security Management Unit Name Reset Access Description LETIMER0 LETIMER0 Secure Access LETIMER0 Secure Access 10.5.11 SMU_PPUFS - Fault Status Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PPUFSPERIPHID...
  • Page 236: Smu_Bmpupatd0 - Privileged Attribute

    Reference Manual SMU - Security Management Unit 10.5.12 SMU_BMPUPATD0 - Privileged Attribute Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SEDMA SE mailbox DMA privileged mode...
  • Page 237: Smu_Bmpusatd0 - Secure Attribute

    Reference Manual SMU - Security Management Unit 10.5.13 SMU_BMPUSATD0 - Secure Attribute Offset Bit Position 0x170 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SEDMA MCU to SE mailbox DMA secure mode...
  • Page 238: Smu_Bmpufs - Fault Status

    Reference Manual SMU - Security Management Unit 10.5.14 SMU_BMPUFS - Fault Status Offset Bit Position 0x250 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions BMPUFSMASTERID Fault...
  • Page 239: Smu_Esaurtypes0 - Region Types 0

    Reference Manual SMU - Security Management Unit 10.5.16 SMU_ESAURTYPES0 - Region Types 0 Offset Bit Position 0x260 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions ESAUR3NS...
  • Page 240: Smu_Esaumrb01 - Movable Region Boundary

    Reference Manual SMU - Security Management Unit 10.5.18 SMU_ESAUMRB01 - Movable Region Boundary Offset Bit Position 0x270 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:12...
  • Page 241: Smu_Esaumrb45 - Movable Region Boundary

    Reference Manual SMU - Security Management Unit 10.5.20 SMU_ESAUMRB45 - Movable Region Boundary Offset Bit Position 0x280 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:12...
  • Page 242: Se - Secure Element Subsystem

    Reference Manual SE - Secure Element Subsystem 11. SE - Secure Element Subsystem Quick Facts What? The Secure Element Subsystem encapsulates se- curity peripherals providing both improved system security and ease of use. Why? Isolation of security hardware from the Cortex-M33 protects the SE system from exploits that target the main CPU.
  • Page 243: Secure Debug

    Reference Manual SE - Secure Element Subsystem 11.3.1 Secure Debug The SE provides a secure debug unlock function that allows users to grant debug access to locked devices on a device by device ba- sis. To use this function the device must be programmed with a public encryption key (PK) by the user. To unlock a device, a unique identifier must be read out and signed by the private key associated with PK creating an unlock token.
  • Page 244: Register Map

    Reference Manual SE - Secure Element Subsystem 11.4.3 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 SEMAILBOX_DATAx RX/TX FIFO DATA 0x040 SEMAILBOX_TX_STATUS TX Status 0x044 SEMAILBOX_RX_STATUS RX Status 0x048 SEMAILBOX_TX_PROT TX Protection 0x04C SEMAILBOX_RX_PROT...
  • Page 245 Reference Manual SE - Secure Element Subsystem 11.4.4.2 SEMAILBOX_TX_STATUS - TX Status Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TXERROR TX Error Flag...
  • Page 246 Reference Manual SE - Secure Element Subsystem 11.4.4.3 SEMAILBOX_RX_STATUS - RX Status Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RXERROR RX Error Flag...
  • Page 247 Reference Manual SE - Secure Element Subsystem 11.4.4.4 SEMAILBOX_TX_PROT - TX Protection Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:24 USER User Bits User bits (reserved) NONSEC Non-Secure Access Non-Seccure access bit (reserved) PRIV Privileged Access Priveledge Access bit (reserved) UNPROTECTED Unprotected...
  • Page 248 Reference Manual SE - Secure Element Subsystem 11.4.4.5 SEMAILBOX_RX_PROT - RX Protection Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:24 USER User Bits User bits (reserved) NONSEC Non-Secure Access Non-Seccure access bit (reserved) PRIV Privileged Access Priveledge Access bit (reserved) UNPROTECTED Unprotected...
  • Page 249 Reference Manual SE - Secure Element Subsystem 11.4.4.6 SEMAILBOX_TX_HEADER - TX Header Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions UNPROTECTED Unprotected...
  • Page 250 Reference Manual SE - Secure Element Subsystem 11.4.4.7 SEMAILBOX_RX_HEADER - RX Header Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions UNPROTECTED Unprotected...
  • Page 251: Emu - Energy Management Unit

    Reference Manual EMU - Energy Management Unit 12. EMU - Energy Management Unit Quick Facts What? The EMU (Energy Management Unit) handles the different low energy modes in EFR32xG21 Why? The need for performance and peripheral functions varies over time in most applications. By efficiently scaling the available resources in real time to match the demands of the application, the energy con- sumption can be kept at a minimum.
  • Page 252: Features

    Reference Manual EMU - Energy Management Unit 12.2 Features The primary features of the EMU are listed below: • Energy Modes control • Entry into EM4 • Configuration of regulators and clocks for each Energy Mode • Configuration of various EM4 wake-up conditions •...
  • Page 253: Functional Description

    Reference Manual EMU - Energy Management Unit 12.3 Functional Description The EMU is responsible for managing the wide range of energy modes available in EFR32xG21. The block works in harmony with the entire platform to easily transition between energy modes in the most efficient manner possible. The following diagram Figure 12.1 EMU Overview on page 253, shows the relative connectivity to the various blocks in the system.
  • Page 254: Energy Modes

    Reference Manual EMU - Energy Management Unit 12.3.1 Energy Modes EFR32xG21 features five main energy modes, referred to as Energy Mode 0 ( EM0) through Energy Mode 4 ( EM4). The Cortex-M33 is only available for program execution in EM0. In EM0 Active/EM1 Sleep any peripheral function can be enabled. EM2 through EM4, also referred to as low energy modes, provide a significantly reduced energy consumption while still allowing a rich set of peripheral func- tionality.
  • Page 255 Reference Manual EMU - Energy Management Unit EM0 Active/EM1 Sleep High Frequency Oscillators Available (HFXO,HFRCODPLL) and Clocks (BUSCLK, HCLK, PCLK, RADIOCLK, EM01GRPACLK) EM2/3 High Frequency Oscil- Available Available Available lator (HFRCOEM23) and ADC Clock (IADCCLK) Low Frequency Oscillators Available Available Available (LFRCO, LFXO) Low Energy Clocks...
  • Page 256 Reference Manual EMU - Energy Management Unit EM0 Active/EM1 Sleep Note: 1. Approximate time. Refer to the data sheet 2. Leaving the debugger connected when in EM2 or EM3 will cause the system to enter a higher power EM2 mode in which the high frequency clocks are still enabled and certain core functionality is still powered-up in order to maintain debug-functionality.
  • Page 257 Reference Manual EMU - Energy Management Unit 12.3.1.3 EM2 This is the first level into the low power energy modes. Most of the high frequency peripherals are disabled or have reduced functionali- ty. Memory and registers retain their values. • Cortex-M33 is in sleep mode. Clocks to the core are off. •...
  • Page 258: Entering Low Energy Modes

    Reference Manual EMU - Energy Management Unit 12.3.1.5 EM4 EM4 is the lowest energy mode of the part. There is no retention except for GPIO PAD state and BURAM values. Wake-up from EM4 requires a reset to the system, returning it back to EM0 •...
  • Page 259: Exiting A Low Energy Mode

    Reference Manual EMU - Energy Management Unit 12.3.2.3 Entry Into EM4 Energy mode EM4 is entered through register access. Software must ensure no modules are active,such as RAC, when entering EM4. EM4CTRL->EM4STATE field must be configured to select Shutoff (EM4S) mode prior to entering EM4. Software may enter EM4 from EM0 by writing the sequence 2,3,2,3,2,3,2,3,2 to EM4CTRL->EM4ENTRY bit field.
  • Page 260: Brown Out Detector (Bod)

    Reference Manual EMU - Energy Management Unit 12.3.4 Brown Out Detector (BOD) Brown out detectors ensure that the minimum supply required for the chip to operate properly and safely is provided to the EFR32xG21. Once triggered, a BOD will generate a system reset. Each BOD raw output is visible via the EMU_ANASTATUS register and can also be routed to a GPIO via PRS for observability (see EMU PRS section for more details).
  • Page 261: Reset Management Unit

    Reference Manual EMU - Energy Management Unit 12.3.5 Reset Management Unit EMU RMU (Reset Management Unit) ensures correct reset operation. It is responsible for connecting the different reset sources to the reset lines of the EFR32xG21. After reset, the M33 loads the stack pointer and program entry point from memory and start execution. Secure Tamper Detect Element...
  • Page 262: Temperature Sensor

    Reference Manual EMU - Energy Management Unit User can determine the cause of the last reset by querying the EMU_RMURSTCAUSE register. Once read, EMU_RMURSTCAUSE should be cleared via EMU_CMD_RCCLR. Table 12.5. Reset Sources Summary RSTCAU Name Type Can be Disabled? Description SE Bit Hard...
  • Page 263: Register Resets

    Reference Manual EMU - Energy Management Unit 12.3.7 Register Resets Each EMU register requires retaining state in various energy modes and power transitions and will consequently need to be reset with a different condition. The following reset conditions will apply to the appropriate set of registers as marked in the Register Description table.
  • Page 264: Register Map

    Reference Manual EMU - Energy Management Unit 12.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x010 EMU_DECBOD DECOUPLE LVBOD Control register 0x020 EMU_BOD3SENSE BOD3SENSE Control register 0x060 EMU_LOCK EMU Configuration lock register 0x064 EMU_IF RWH INTFLAG...
  • Page 265 Reference Manual EMU - Energy Management Unit Offset Name Type Description 0x2020 EMU_BOD3SENSE_CLR BOD3SENSE Control register 0x2060 EMU_LOCK_CLR EMU Configuration lock register 0x2064 EMU_IF_CLR RWH INTFLAG Interrupt Flags 0x2068 EMU_IEN_CLR Interrupt Enables 0x206C EMU_EM4CTRL_CLR EM4 Control 0x2070 EMU_CMD_CLR EMU Command register 0x2074 EMU_CTRL_CLR EMU Control register...
  • Page 266: Register Description

    Reference Manual EMU - Energy Management Unit 12.5 Register Description 12.5.1 EMU_DECBOD - DECOUPLE LVBOD Control register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DECOVMBODMASK...
  • Page 267: Emu_Bod3Sense - Bod3Sense Control Register

    Reference Manual EMU - Energy Management Unit 12.5.2 EMU_BOD3SENSE - BOD3SENSE Control register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions IOVDD1BODEN...
  • Page 268: Emu_If - Interrupt Flags

    Reference Manual EMU - Energy Management Unit 12.5.4 EMU_IF - Interrupt Flags Offset Bit Position 0x064 Reset Access Name Name Reset Access Description TEMPHIGH Temperature high Interrupt flag Measured temperature above threshold TEMPLOW Temperature low Interrupt flag Measured temperature below threshold TEMP Temperature Interrupt flag Temperature Update...
  • Page 269: Emu_Ien - Interrupt Enables

    Reference Manual EMU - Energy Management Unit 12.5.5 EMU_IEN - Interrupt Enables Offset Bit Position 0x068 Reset Access Name Name Reset Access Description TEMPHIGH Temperature high Interrupt enable Measured temperature above threshold Interrupt enable TEMPLOW Temperature low Interrupt enable Measured temperature below threshold Interrupt enable TEMP Temperature Interrupt enable Temperature Update Interrupt enable...
  • Page 270: Emu_Em4Ctrl - Em4 Control

    Reference Manual EMU - Energy Management Unit 12.5.6 EMU_EM4CTRL - EM4 Control Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions EM4IORETMODE EM4 IO retention mode...
  • Page 271: Emu_Cmd - Emu Command Register

    Reference Manual EMU - Energy Management Unit 12.5.7 EMU_CMD - EMU Command register Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RSTCAUSECLR...
  • Page 272: Emu_Ctrl - Emu Control Register

    Reference Manual EMU - Energy Management Unit 12.5.8 EMU_CTRL - EMU Control register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FLASHPWRUPONDE-...
  • Page 273: Emu_Templimits - Emu Temperature Thresholds

    Reference Manual EMU - Energy Management Unit 12.5.9 EMU_TEMPLIMITS - EMU Temperature thresholds Offset Bit Position 0x078 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 24:16...
  • Page 274: Emu_Status - Emu Status Register

    Reference Manual EMU - Energy Management Unit 12.5.10 EMU_STATUS - EMU Status register Offset Bit Position 0x084 Reset Access Name Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions EM2ENTERED...
  • Page 275: Emu_Temp - Temperature

    Reference Manual EMU - Energy Management Unit 12.5.11 EMU_TEMP - Temperature Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 10:2 TEMP...
  • Page 276: Emu_Rstctrl - Reset Management Control Register

    Reference Manual EMU - Energy Management Unit 12.5.12 EMU_RSTCTRL - Reset Management Control register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SELOCKUPRMODE...
  • Page 277 Reference Manual EMU - Energy Management Unit Name Reset Access Description ENABLED The entire device is reset except some EMU registers AVDDBODRMODE Enable AVDD BOD reset LEBOD1 Reset Mode. AVDD monitoring. BOD must be trimmed before it is used as a reset source. Value Mode Description...
  • Page 278: Emu_Rstcause - Reset Cause

    Reference Manual EMU - Energy Management Unit 12.5.13 EMU_RSTCAUSE - Reset cause Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SELOCKUP SE Lockup Reset...
  • Page 279: Emu_Dgif - Interrupt Flags Debug

    Reference Manual EMU - Energy Management Unit Name Reset Access Description EM4 Wakeup Reset Last reset was a EM4 Wakeup Pin Reset Last reset was a Pin reset Power On Reset Last reset was a Power On Reset 12.5.14 EMU_DGIF - Interrupt Flags Debug Offset Bit Position 0x0A0...
  • Page 280: Emu_Dgien - Interrupt Enables Debug

    Reference Manual EMU - Energy Management Unit 12.5.15 EMU_DGIEN - Interrupt Enables Debug Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description TEMPHIGH Temperature high Interrupt enable Measured temperature above threshold TEMPLOW Temperature low Interrupt enable Measured temperature below threshold TEMP Temperature Interrupt enable Temperature Update...
  • Page 281: Emu_Seif - Interrupt Flags Secure Element

    Reference Manual EMU - Energy Management Unit 12.5.16 EMU_SEIF - Interrupt Flags Secure Element Offset Bit Position 0x0A8 Reset Access Name Name Reset Access Description TEMPHIGH Temperature low Interrupt flag Measured temperature above threshold TEMPLOW Temperature Interrupt flag Measured temperature below threshold TEMP Temperature Interrupt flag Temperature Update...
  • Page 282: Prs - Peripheral Reflex System

    Reference Manual PRS - Peripheral Reflex System 13. PRS - Peripheral Reflex System Quick Facts What? The PRS (Peripheral Reflex System) allows configu- rable, fast, and autonomous communication be- tween peripherals. Why? Events and signals from one peripheral can be used as input signals to trigger actions in other peripher- als.
  • Page 283: Functional Description

    Reference Manual PRS - Peripheral Reflex System 13.3 Functional Description The PRS contains 12 asynchronous and 4 synchronous reflex channels. An overview of an asynchronous PRS reflex channel is shown Figure 13.1 PRS Asynchronous Channel Overview on page 283. Synchronous channels are similar but do not include the configura- ble logic block or SWLEVEL / SWPULSE features.
  • Page 284: Configurable Logic

    Reference Manual PRS - Peripheral Reflex System 13.3.2 Configurable Logic The configurable logic feature enables a PRS channel to perform logic operations on the signal coming from the selected producer. Every asynchronous channel has a configurable logic block that can be programmed using the FNSEL field in the asynchronous chan- nel control register.
  • Page 285: Producers

    Reference Manual PRS - Peripheral Reflex System FNSEL value Implemented Function A OR (NOT B) (NOT A) OR B A OR B The default value of FNSEL is 0xC, meaning that the input from the selected producer goes through unchanged. This feature can be used to combine multiple channels to get even more complex functions.
  • Page 286 Reference Manual PRS - Peripheral Reflex System 13.3.3.1 Producer Details Table 13.4. Synchronous PRS Producers Peripheral SOURCESEL Signal SIGSEL TIMER0 TIMER0 (0x01) TIMER1 TIMER1 (0x02) IADC0 IADC0 (0x03) SCANENTRYDONE SCANTABLEDONE SINGLEDONE TIMER2 TIMER2 (0x04) TIMER3 TIMER3 (0x05) Table 13.5. Asynchronous PRS Producers Peripheral SOURCESEL Signal...
  • Page 287 Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL RTCC RTCC (0x03) CCV0 CCV1 CCV2 BURTC BURTC (0x04) COMP OVERFLOW GPIO GPIO (0x05) PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 ACMP0 ACMP0 (0x06) ACMP1 ACMP1 (0x07) CMUL (0x08) CLKOUT0 CLKOUT1 CLKOUT2...
  • Page 288 Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL USART2 USART2 (0x22) IRTX RXDATA TIMER0 TIMER0 (0x23) TIMER1 TIMER1 (0x24) TIMER2 TIMER2 (0x25) TIMER3 TIMER3 (0x26) CORE CORE (0x27) CTIOUT0 CTIOUT1 CTIOUT2 CTIOUT3 AGCL (0x28) CCAREQ AGC (0x29) RSSIDONE silabs.com | Building a more connected world.
  • Page 289 Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL MODEM MODEML (0x2B) ADVANCE ANT0 ANT1 COHDSADET COHDSALIVE DCLK DOUT FRAMEDET MODEM (0x2C) FRAMESENT LOWCORR LRDSADET LRDSALIVE NEWSYMBOL NEWWND POSTPONE PREDET MODEMH (0x2D) PRESENT RSSIJUMP SYNCSENT TIMDET WEAK FRC (0x2E) DCLK DOUT PROTIMER...
  • Page 290: Consumers

    Reference Manual PRS - Peripheral Reflex System 13.3.4 Consumers Consumer peripherals can be set to listen to a PRS channel and perform an action based on the signal received on that channel. This is done by programming the PRSSEL or SPRSSEL in the consumer registers. SPRSSEL is only present for signals with the ability to listen to synchronous channels.
  • Page 291: Register Map

    Reference Manual PRS - Peripheral Reflex System 13.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PRS_IPVERSION IP version ID 0x008 PRS_ASYNC_SWPULSE Software Pulse Register 0x00C PRS_ASYNC_SWLEVEL Software Level Register 0x010 PRS_ASYNC_PEEK Async Channel Values...
  • Page 292 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x0E4 PRS_CONSUMER_SE_TAM- SE TAMPERSRC1 Consumer Selection PERSRC1 0x0E8 PRS_CONSUMER_SE_TAM- SE TAMPERSRC2 Consumer Selection PERSRC2 0x0EC PRS_CONSUMER_SE_TAM- SE TAMPERSRC3 Consumer Selection PERSRC3 0x0F0 PRS_CONSUMER_SE_TAM- SE TAMPERSRC4 Consumer Selection PERSRC4 0x0F4 PRS_CONSUMER_SE_TAM- SE TAMPERSRC5 Consumer Selection PERSRC5...
  • Page 293 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x14C PRS_CONSUMER_TIM- TIMER2 CC0 Consumer Selection ER2_CC0 0x150 PRS_CONSUMER_TIM- TIMER2 CC1 Consumer Selection ER2_CC1 0x154 PRS_CONSUMER_TIM- TIMER2 CC2 Consumer Selection ER2_CC2 0x158 PRS_CONSUMER_TIMER2_DTI TIMER2 DTI Consumer Selection 0x15C PRS_CONSUMER_TIM- TIMER2 DTIFS1 Consumer Selection ER2_DTIFS1 0x160...
  • Page 294 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x1B4 PRS_CONSUM- WDOG1 SRC0 Consumer Selection ER_WDOG1_SRC0 0x1B8 PRS_CONSUM- WDOG1 SRC1 Consumer Selection ER_WDOG1_SRC1 0x1000 PRS_IPVERSION_SET IP version ID 0x1008 PRS_ASYNC_SWPULSE_SET Software Pulse Register 0x100C PRS_ASYNC_SWLEVEL_SET Software Level Register 0x1010 PRS_ASYNC_PEEK_SET Async Channel Values...
  • Page 295 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x10D0 PRS_CONSUM- RTCC CC0 Consumer Selection ER_RTCC_CC0_SET 0x10D4 PRS_CONSUM- RTCC CC1 Consumer Selection ER_RTCC_CC1_SET 0x10D8 PRS_CONSUM- RTCC CC2 Consumer Selection ER_RTCC_CC2_SET 0x10E0 PRS_CONSUMER_SE_TAM- SE TAMPERSRC0 Consumer Selection PERSRC0_SET 0x10E4 PRS_CONSUMER_SE_TAM- SE TAMPERSRC1 Consumer Selection PERSRC1_SET...
  • Page 296 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x1138 PRS_CONSUMER_TIM- TIMER1 CC1 Consumer Selection ER1_CC1_SET 0x113C PRS_CONSUMER_TIM- TIMER1 CC2 Consumer Selection ER1_CC2_SET 0x1140 PRS_CONSUMER_TIM- TIMER1 DTI Consumer Selection ER1_DTI_SET 0x1144 PRS_CONSUMER_TIM- TIMER1 DTIFS1 Consumer Selection ER1_DTIFS1_SET 0x1148 PRS_CONSUMER_TIM- TIMER1 DTIFS2 Consumer Selection ER1_DTIFS2_SET...
  • Page 297 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x1194 PRS_CONSUM- USART1 RX Consumer Selection ER_USART1_RX_SET 0x1198 PRS_CONSUM- USART1 TRIGGER Consumer Selection ER_USART1_TRIGGER_SET 0x119C PRS_CONSUM- USART2 CLK Consumer Selection ER_USART2_CLK_SET 0x11A0 PRS_CONSUM- USART2 IR Consumer Selection ER_USART2_IR_SET 0x11A4 PRS_CONSUM- USART2 RX Consumer Selection ER_USART2_RX_SET...
  • Page 298 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x207C PRS_CONSUMER_LETIM- LETIMER STOP Consumer Selection ER0_STOP_CLR 0x2080 PRS_CONSUMER_MO- MODEM DIN Consumer Selection DEM_DIN_CLR 0x20B8 PRS_CONSUM- RAC CLR Consumer Selection ER_RAC_CLR_CLR 0x20BC PRS_CONSUM- RAC FORCETX Consumer Selection ER_RAC_FORCETX_CLR 0x20C0 PRS_CONSUM- RAC RXDIS Consumer Selection ER_RAC_RXDIS_CLR 0x20C4 PRS_CONSUM-...
  • Page 299 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x2118 PRS_CONSUM- M33 Consumer Selection ER_CORE_M33RXEV_CLR 0x211C PRS_CONSUMER_TIM- TIMER0 CC0 Consumer Selection ER0_CC0_CLR 0x2120 PRS_CONSUMER_TIM- TIMER0 CC1 Consumer Selection ER0_CC1_CLR 0x2124 PRS_CONSUMER_TIM- TIMER0 CC2 Consumer Selection ER0_CC2_CLR 0x2128 PRS_CONSUMER_TIM- TIMER0 DTI Consumer Selection ER0_DTI_CLR 0x212C PRS_CONSUMER_TIM-...
  • Page 300 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x2174 PRS_CONSUMER_TIM- TIMER3 DTIFS1 Consumer Selection ER3_DTIFS1_CLR 0x2178 PRS_CONSUMER_TIM- TIMER3 DTIFS2 Consumer Selection ER3_DTIFS2_CLR 0x217C PRS_CONSUM- USART0 CLK Consumer Selection ER_USART0_CLK_CLR 0x2180 PRS_CONSUM- USART0 IR Consumer Selection ER_USART0_IR_CLR 0x2184 PRS_CONSUM- USART0 RX Consumer Selection ER_USART0_RX_CLR...
  • Page 301 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x305C PRS_CONSUMER_CMU_CAL- CMU CALUP Consumer Selection UP_TGL 0x3064 PRS_CONSUM- IADC0 SCANTRIGGER Consumer Selection ER_IADC0_SCANTRIG- GER_TGL 0x3068 PRS_CONSUMER_IADC0_SIN- IADC0 SINGLETRIGGER Consumer Selection GLETRIGGER_TGL 0x306C PRS_CONSUMER_LDMAX- DMAREQ0 Consumer Selection BAR_DMAREQ0_TGL 0x3070 PRS_CONSUMER_LDMAX- DMAREQ1 Consumer Selection BAR_DMAREQ1_TGL...
  • Page 302 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x30F4 PRS_CONSUMER_SE_TAM- SE TAMPERSRC5 Consumer Selection PERSRC5_TGL 0x30F8 PRS_CONSUMER_SE_TAM- SE TAMPERSRC6 Consumer Selection PERSRC6_TGL 0x30FC PRS_CONSUMER_SE_TAM- SE TAMPERSRC7 Consumer Selection PERSRC7_TGL 0x3108 PRS_CONSUM- CTI0 Consumer Selection ER_CORE_CTIIN0_TGL 0x310C PRS_CONSUM- CTI1 Consumer Selection ER_CORE_CTIIN1_TGL 0x3110...
  • Page 303 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x3158 PRS_CONSUMER_TIM- TIMER2 DTI Consumer Selection ER2_DTI_TGL 0x315C PRS_CONSUMER_TIM- TIMER2 DTIFS1 Consumer Selection ER2_DTIFS1_TGL 0x3160 PRS_CONSUMER_TIM- TIMER2 DTIFS2 Consumer Selection ER2_DTIFS2_TGL 0x3164 PRS_CONSUMER_TIM- TIMER3 CC0 Consumer Selection ER3_CC0_TGL 0x3168 PRS_CONSUMER_TIM- TIMER3 CC1 Consumer Selection ER3_CC1_TGL...
  • Page 304: Register Description

    Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x31B4 PRS_CONSUM- WDOG1 SRC0 Consumer Selection ER_WDOG1_SRC0_TGL 0x31B8 PRS_CONSUM- WDOG1 SRC1 Consumer Selection ER_WDOG1_SRC1_TGL 13.5 Register Description 13.5.1 PRS_IPVERSION - IP version ID Offset Bit Position 0x000 Reset Access Name Name Reset...
  • Page 305: Prs_Async_Swpulse - Software Pulse Register

    Reference Manual PRS - Peripheral Reflex System 13.5.2 PRS_ASYNC_SWPULSE - Software Pulse Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CH11PULSE...
  • Page 306: Prs_Async_Swlevel - Software Level Register

    Reference Manual PRS - Peripheral Reflex System 13.5.3 PRS_ASYNC_SWLEVEL - Software Level Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CH11LEVEL...
  • Page 307: Prs_Async_Peek - Async Channel Values

    Reference Manual PRS - Peripheral Reflex System 13.5.4 PRS_ASYNC_PEEK - Async Channel Values Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CH11VAL...
  • Page 308: Prs_Sync_Peek - Sync Channel Values

    Reference Manual PRS - Peripheral Reflex System 13.5.5 PRS_SYNC_PEEK - Sync Channel Values Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CH3VAL...
  • Page 309: Prs_Async_Chx_Ctrl - Async Channel Control Register

    Reference Manual PRS - Peripheral Reflex System 13.5.6 PRS_ASYNC_CHx_CTRL - Async Channel Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 310: Prs_Sync_Chx_Ctrl - Sync Channel Control Register

    Reference Manual PRS - Peripheral Reflex System Name Reset Access Description Select signal input for asynchronous PRS channel. See Asynchronous Producers table for details. Value Mode Description NONE 13.5.7 PRS_SYNC_CHx_CTRL - Sync Channel Control Register Offset Bit Position 0x048 Reset Access Name Name...
  • Page 311: Prs_Consumer_Cmu_Caldn - Cmu Caldn Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.8 PRS_CONSUMER_CMU_CALDN - CMU CALDN Consumer Selection Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 312: Prs_Consumer_Iadc0_Scantrigger - Iadc0 Scantrigger Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.10 PRS_CONSUMER_IADC0_SCANTRIGGER - IADC0 SCANTRIGGER Consumer Selection Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 313: Prs_Consumer_Ldmaxbar_Dmareq0 - Dmareq0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.12 PRS_CONSUMER_LDMAXBAR_DMAREQ0 - DMAREQ0 Consumer Selection Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 314: Prs_Consumer_Letimer0_Clear - Letimer Clear Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.14 PRS_CONSUMER_LETIMER0_CLEAR - LETIMER CLEAR Consumer Selection Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 315: Prs_Consumer_Letimer0_Stop - Letimer Stop Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.16 PRS_CONSUMER_LETIMER0_STOP - LETIMER STOP Consumer Selection Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 316: Prs_Consumer_Rac_Clr - Rac Clr Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.18 PRS_CONSUMER_RAC_CLR - RAC CLR Consumer Selection Offset Bit Position 0x0B8 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 317: Prs_Consumer_Rac_Rxdis - Rac Rxdis Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.20 PRS_CONSUMER_RAC_RXDIS - RAC RXDIS Consumer Selection Offset Bit Position 0x0C0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 318: Prs_Consumer_Rac_Seq - Rac Seq Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.22 PRS_CONSUMER_RAC_SEQ - RAC SEQ Consumer Selection Offset Bit Position 0x0C8 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 319: Prs_Consumer_Rtcc_Cc0 - Rtcc Cc0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.24 PRS_CONSUMER_RTCC_CC0 - RTCC CC0 Consumer Selection Offset Bit Position 0x0D0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 320: Prs_Consumer_Rtcc_Cc2 - Rtcc Cc2 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.26 PRS_CONSUMER_RTCC_CC2 - RTCC CC2 Consumer Selection Offset Bit Position 0x0D8 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 321: Prs_Consumer_Se_Tampersrc1 - Se Tampersrc1 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.28 PRS_CONSUMER_SE_TAMPERSRC1 - SE TAMPERSRC1 Consumer Selection Offset Bit Position 0x0E4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 322: Prs_Consumer_Se_Tampersrc3 - Se Tampersrc3 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.30 PRS_CONSUMER_SE_TAMPERSRC3 - SE TAMPERSRC3 Consumer Selection Offset Bit Position 0x0EC Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 323: Prs_Consumer_Se_Tampersrc5 - Se Tampersrc5 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.32 PRS_CONSUMER_SE_TAMPERSRC5 - SE TAMPERSRC5 Consumer Selection Offset Bit Position 0x0F4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 324: Prs_Consumer_Se_Tampersrc7 - Se Tampersrc7 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.34 PRS_CONSUMER_SE_TAMPERSRC7 - SE TAMPERSRC7 Consumer Selection Offset Bit Position 0x0FC Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 325: Prs_Consumer_Core_Ctiin1 - Cti1 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.36 PRS_CONSUMER_CORE_CTIIN1 - CTI1 Consumer Selection Offset Bit Position 0x10C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 326: Prs_Consumer_Core_Ctiin3 - Cti3 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.38 PRS_CONSUMER_CORE_CTIIN3 - CTI3 Consumer Selection Offset Bit Position 0x114 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 327: Prs_Consumer_Timer0_Cc0 - Timer0 Cc0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.40 PRS_CONSUMER_TIMER0_CC0 - TIMER0 CC0 Consumer Selection Offset Bit Position 0x11C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 328: Prs_Consumer_Timer0_Cc2 - Timer0 Cc2 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.42 PRS_CONSUMER_TIMER0_CC2 - TIMER0 CC2 Consumer Selection Offset Bit Position 0x124 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 329: Prs_Consumer_Timer0_Dtifs1 - Timer0 Dtifs1 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.44 PRS_CONSUMER_TIMER0_DTIFS1 - TIMER0 DTIFS1 Consumer Selection Offset Bit Position 0x12C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 330: Prs_Consumer_Timer1_Cc0 - Timer1 Cc0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.46 PRS_CONSUMER_TIMER1_CC0 - TIMER1 CC0 Consumer Selection Offset Bit Position 0x134 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 331: Prs_Consumer_Timer1_Cc2 - Timer1 Cc2 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.48 PRS_CONSUMER_TIMER1_CC2 - TIMER1 CC2 Consumer Selection Offset Bit Position 0x13C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 332: Prs_Consumer_Timer1_Dtifs1 - Timer1 Dtifs1 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.50 PRS_CONSUMER_TIMER1_DTIFS1 - TIMER1 DTIFS1 Consumer Selection Offset Bit Position 0x144 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 333: Prs_Consumer_Timer2_Cc0 - Timer2 Cc0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.52 PRS_CONSUMER_TIMER2_CC0 - TIMER2 CC0 Consumer Selection Offset Bit Position 0x14C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 334: Prs_Consumer_Timer2_Cc2 - Timer2 Cc2 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.54 PRS_CONSUMER_TIMER2_CC2 - TIMER2 CC2 Consumer Selection Offset Bit Position 0x154 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 335: Prs_Consumer_Timer2_Dtifs1 - Timer2 Dtifs1 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.56 PRS_CONSUMER_TIMER2_DTIFS1 - TIMER2 DTIFS1 Consumer Selection Offset Bit Position 0x15C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 336: Prs_Consumer_Timer3_Cc0 - Timer3 Cc0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.58 PRS_CONSUMER_TIMER3_CC0 - TIMER3 CC0 Consumer Selection Offset Bit Position 0x164 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 337: Prs_Consumer_Timer3_Cc2 - Timer3 Cc2 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.60 PRS_CONSUMER_TIMER3_CC2 - TIMER3 CC2 Consumer Selection Offset Bit Position 0x16C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SPRSSEL...
  • Page 338: Prs_Consumer_Timer3_Dtifs1 - Timer3 Dtifs1 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.62 PRS_CONSUMER_TIMER3_DTIFS1 - TIMER3 DTIFS1 Consumer Selection Offset Bit Position 0x174 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 339: Prs_Consumer_Usart0_Clk - Usart0 Clk Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.64 PRS_CONSUMER_USART0_CLK - USART0 CLK Consumer Selection Offset Bit Position 0x17C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 340: Prs_Consumer_Usart0_Rx - Usart0 Rx Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.66 PRS_CONSUMER_USART0_RX - USART0 RX Consumer Selection Offset Bit Position 0x184 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 341: Prs_Consumer_Usart1_Clk - Usart1 Clk Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.68 PRS_CONSUMER_USART1_CLK - USART1 CLK Consumer Selection Offset Bit Position 0x18C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 342: Prs_Consumer_Usart1_Rx - Usart1 Rx Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.70 PRS_CONSUMER_USART1_RX - USART1 RX Consumer Selection Offset Bit Position 0x194 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 343: Prs_Consumer_Usart2_Clk - Usart2 Clk Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.72 PRS_CONSUMER_USART2_CLK - USART2 CLK Consumer Selection Offset Bit Position 0x19C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 344: Prs_Consumer_Usart2_Rx - Usart2 Rx Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.74 PRS_CONSUMER_USART2_RX - USART2 RX Consumer Selection Offset Bit Position 0x1A4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 345: Prs_Consumer_Wdog0_Src0 - Wdog0 Src0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.76 PRS_CONSUMER_WDOG0_SRC0 - WDOG0 SRC0 Consumer Selection Offset Bit Position 0x1AC Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 346: Prs_Consumer_Wdog1_Src0 - Wdog1 Src0 Consumer Selection

    Reference Manual PRS - Peripheral Reflex System 13.5.78 PRS_CONSUMER_WDOG1_SRC0 - WDOG1 SRC0 Consumer Selection Offset Bit Position 0x1B4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PRSSEL...
  • Page 347: Gpcrc - General Purpose Cyclic Redundancy Check

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14. GPCRC - General Purpose Cyclic Redundancy Check Quick Facts What? The GPCRC is an error-detecting module commonly used in digital networks and storage systems to de- tect accidental changes to data. Why? The GPCRC module can detect errors in data, giv- ing a higher system reliability and robustness.
  • Page 348: Functional Description

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.3 Functional Description An overview of the GPCRC module is shown in Figure 14.1 GPCRC Overview on page 348. GPCRC Module DATAREV bit reversal DATA byte reversal DATABYTEREV INPUTDATA byte byte-level reorder Hardware CRC reversal...
  • Page 349: Polynomial Specification

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.3.1 Polynomial Specification POLYSEL in GPCRC_CTRL selects between 32-bit and 16-bit polynomial functions. When a 32-bit polynomial is selected, the fixed IEEE 802.3 polynomial(0x04C11DB7) is used. When a 16-bit polynomial is selected, any valid polynomial can be defined by the user in GPCRC_POLY.
  • Page 350: Byte-Level Bit Reversal And Byte Reordering

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.3.5 Byte-Level Bit Reversal and Byte Reordering The byte-level bit reversal and byte reordering operations occur before the data is used in the CRC calculation. Byte reordering can occur on words or half words. The hardware ignores the BYTEREVERSE field with any byte writes or operations with byte mode ena- bled (BYTEMODE = 1), but the bit reversal settings (BITREVERSE) are still applied to the byte.
  • Page 351 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Byte 3 Byte 2 Byte 1 Byte 0 Input data is big endian, MSB-first BYTEREVERSE = 1 8'h00 8'h00 Byte 0 Byte 1 BITREVERSE = 1 8'h00 8'h00 Byte 0 Byte 1 Data is now 16-bit little endian, LSB-first for CRC calculation...
  • Page 352 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Input Width(bits) BYTEREVERSE Setting BITREVERSE Setting Input to CRC Calculation Notes: 1. X indicates a "don't care". 2. Bn is the byte field within the word. 3. 'Bn is the bit-reversed byte field within the word. silabs.com | Building a more connected world.
  • Page 353: Register Map

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPCRC_IPVERSION IP Version ID 0x004 GPCRC_EN CRC Enable 0x008 GPCRC_CTRL Control Register 0x00C GPCRC_CMD Command Register...
  • Page 354: Register Description

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Offset Name Type Description 0x2024 GPCRC_DATA_CLR R(r)H CRC Data Register 0x2028 GPCRC_DATAREV_CLR R(r)H CRC Data Reverse Register 0x202C GPCRC_DATABYTEREV_CLR R(r)H CRC Data Byte Reverse Register 0x3000 GPCRC_IPVERSION_TGL IP Version ID 0x3004 GPCRC_EN_TGL CRC Enable 0x3008...
  • Page 355: Gpcrc_En - Crc Enable

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.2 GPCRC_EN - CRC Enable Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CRC Enable...
  • Page 356: Gpcrc_Ctrl - Control Register

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.3 GPCRC_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions AUTOINIT...
  • Page 357: Gpcrc_Cmd - Command Register

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 14.5.4 GPCRC_CMD - Command Register Offset Bit Position 0x00C Reset Access Name...
  • Page 358: Gpcrc_Poly - Crc Polynomial Value

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.6 GPCRC_POLY - CRC Polynomial Value Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0...
  • Page 359: Gpcrc_Inputdatahword - Input 16-Bit Data Register

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.8 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0...
  • Page 360: Gpcrc_Data - Crc Data Register

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.10 GPCRC_DATA - CRC Data Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 DATA R(r) CRC Data Register CRC Data Register, read only. The CRC data register may still be indirectly written from software, by writing the INIT register and then issue an INITIALIZE command.
  • Page 361: Gpcrc_Databyterev - Crc Data Byte Reverse Register

    Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.12 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:0 DATABYTEREV R(r) Data Byte Reverse Value Byte reversed version of CRC Data register. When a 32-bit CRC polynomial is selected, the bytes are swizzled to {B0, B1, B2, B3}.
  • Page 362: Rtcc - Real Time Clock With Capture

    Reference Manual RTCC - Real Time Clock with Capture 15. RTCC - Real Time Clock with Capture Quick Facts What? The Real Time Clock with Capture (RTCC)) is a 32- bit Real Time Clock ensuring timekeeping in low en- ergy modes. Why? Timekeeping over long time periods while using as little power as possible is required in many low pow-...
  • Page 363: Features

    Reference Manual RTCC - Real Time Clock with Capture 15.2 Features A low frequency oscillator is used as clock signal and the RTCC has three different Capture/Compare channels which can trigger wake- up, generate PRS signalling, or capture system events. 32-bit resolution and selectable pre-scaling allows the system to stay in low energy modes for long periods of time and still maintain reliable timekeeping.
  • Page 364: Rtcc Counter

    Reference Manual RTCC - Real Time Clock with Capture 15.3.1 RTCC Counter The RTCC consists of two counters; the 32-bit main counter, RTCC_CNT, and a 15-bit pre-counter, RTCC_PRECNT. The pre-counter can be used as an independent counter, or to generate a specific frequency for the main counter. In both configurations, the pre-coun- ter can be used to generate compare match events or be captured in the Capture/Compare channels as a result of an external PRS event.
  • Page 365 Reference Manual RTCC - Real Time Clock with Capture Main counter period, T RTCC_CTRL_CNTTICK RTCC_CTRL_CNTPRESC Overflow DIV1 30.5 µs 36.4 hours DIV2 61 µs 72.8 hours DIV4 122 µs 145.6 hours DIV8 244 µs 12 days DIV16 488 µs 24 days DIV32 977 µs 48 days...
  • Page 366: Capture/Compare Channels

    Reference Manual RTCC - Real Time Clock with Capture 15.3.2 Capture/Compare Channels Three capture/compare channels are available in the RTCC. Each channel can be configured as input capture or output compare, by setting the corresponding MODE in the RTCC_CCx_CTRL register. RTCC_CNT RTCC_CC0_OCVALUE RTCC_CC1_OCVALUE...
  • Page 367: Interrupts And Prs Output

    Reference Manual RTCC - Real Time Clock with Capture RTCC_CCx_CFG_COMPBASE = CNT PRECNT Compare match CCx_OCVALUE RTCC_CCx_CFG_COMPBASE = PRECNT 0 14 PRECNT Compare match CCx_OCVALUE Figure 15.4. RTCC Compare Base Illustration Table RTCC Capture/Compare subjects summarizes which registers being subject to comparison for different configurations of RTCC_CTRL_CNTMODE and RTCC_CCx_CTRL_COMPBASE.
  • Page 368: Register Lock

    Reference Manual RTCC - Real Time Clock with Capture 15.3.4 Register Lock To prevent accidental writes to the RTCC registers, the RTCC_LOCK register can be written to any other value than the unlock value. To unlock the register, write the unlock value to RTCC_LOCKKEY. Registers affected by this lock are: •...
  • Page 369: Register Map

    Reference Manual RTCC - Real Time Clock with Capture 15.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RTCC_IPVERSION IP VERSION 0x004 RTCC_EN RW ENABLE Module Enable Register 0x008 RTCC_CFG RW CONFIG Configuration Register 0x00C...
  • Page 370 Reference Manual RTCC - Real Time Clock with Capture Offset Name Type Description 0x2014 RTCC_IF_CLR RWH INTFLAG RTCC Interrupt Flags 0x2018 RTCC_IEN_CLR Interrupt Enable Register 0x201C RTCC_PRECNT_CLR RWH LFSYNC Pre-Counter Value Register 0x2020 RTCC_CNT_CLR RWH LFSYNC Counter Value Register 0x2024 RTCC_COMBCNT_CLR Combined Pre-Counter and Counter Valu...
  • Page 371: Register Description

    Reference Manual RTCC - Real Time Clock with Capture 15.5 Register Description 15.5.1 RTCC_IPVERSION - IP VERSION Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP VERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 372: Rtcc_Cfg - Configuration Register

    Reference Manual RTCC - Real Time Clock with Capture 15.5.3 RTCC_CFG - Configuration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CNTPRESC...
  • Page 373: Rtcc_Cmd - Command Register

    Reference Manual RTCC - Real Time Clock with Capture Name Reset Access Description CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0] CNTCCV1TOP CCV1 top value enable When set, the counter wraps around on a CC1 event PRECNTCCV0TOP Pre-counter CCV0 top value enable. When set, the pre-counter wraps around when PRECNT equals RTCC_CC0_OCVALUE[14:0].
  • Page 374: Rtcc_Status - Status Register

    Reference Manual RTCC - Real Time Clock with Capture 15.5.5 RTCC_STATUS - Status register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RTCCLOCKSTATUS...
  • Page 375: Rtcc_If - Rtcc Interrupt Flags

    Reference Manual RTCC - Real Time Clock with Capture 15.5.6 RTCC_IF - RTCC Interrupt Flags Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CC Channel n Interrupt Flag...
  • Page 376: Rtcc_Ien - Interrupt Enable Register

    Reference Manual RTCC - Real Time Clock with Capture 15.5.7 RTCC_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CC Channel n Interrupt Enable...
  • Page 377: Rtcc_Cnt - Counter Value Register

    Reference Manual RTCC - Real Time Clock with Capture 15.5.9 RTCC_CNT - Counter Value Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:0 Counter Value Gives access to the main counter value of the RTCC. 15.5.10 RTCC_COMBCNT - Combined Pre-Counter and Counter Valu... Offset Bit Position 0x024...
  • Page 378: Rtcc_Syncbusy - Synchronization Busy Register

    Reference Manual RTCC - Real Time Clock with Capture 15.5.11 RTCC_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Sync busy for CNT...
  • Page 379: Rtcc_Ccx_Ctrl - Cc Channel Control Register

    Reference Manual RTCC - Real Time Clock with Capture 15.5.13 RTCC_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions ICEDGE...
  • Page 380: Rtcc_Ccx_Ocvalue - Output Compare Value Register

    Reference Manual RTCC - Real Time Clock with Capture Name Reset Access Description INPUTCAPTURE Input capture OUTPUTCOMPARE Output compare 15.5.14 RTCC_CCx_OCVALUE - Output Compare Value Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:0 Output Compare Value Shows the Compare Value for the channel 15.5.15 RTCC_CCx_ICVALUE - Input Capture Value Register Offset...
  • Page 381: Burtc - Back-Up Real Time Counter

    Reference Manual BURTC - Back-Up Real Time Counter 16. BURTC - Back-Up Real Time Counter Quick Facts What? The BURTC is a 32 bit counter which operates on a low frequency oscillator, and is capable of running in all Energy Modes. Why? It can provide periodic Wakeup events and PRS sig- nals which can be used to wake up peripherals from...
  • Page 382: Functional Description

    Reference Manual BURTC - Back-Up Real Time Counter 16.3 Functional Description An overview of the BURTC module is shown in Figure 16.1 BURTC Overview on page 382. 0xFFFFFFFF BURTC_COMP BURTC_CFG.CNTPRESC Clear BURTC_CFG.COMPTOP Counter Pre-Counter BURTCCLK BURTC_CNT BURTC_PRECNT [31:0] BURTC_COMP COMP PRS output 0xFFFFFFFF Compare...
  • Page 383: Compare Channel

    Reference Manual BURTC - Back-Up Real Time Counter 16.3.4 Counter The BURTC consists of two counters: the 32-bit main counter, BURTC_CNT, and a 15-bit pre-counter, BURTC_PRECNT. The pre- counter is a free running counter clocked by low frequency clock, used to generate a specific frequency for the main counter. The pre- counter will be counting only when the BURTC_CFG.CNTPRESC value is set greater than 0.
  • Page 384: Interrupts

    Reference Manual BURTC - Back-Up Real Time Counter 16.3.6 Interrupts The BURTC has 2 interrupts: one for Overflow and another for for Compare match event. Individual interrupts are enabled by BURTC_IEN register bits, and the respective bits can be used as EM2 wakeup. BURTC_EM4WUEN enables the wakeup enable from EM4 for those events.
  • Page 385: Register Map

    Reference Manual BURTC - Back-Up Real Time Counter 16.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 BURTC_IPVERSION IP version ID 0x004 BURTC_EN RW ENABLE Module Enable Register 0x008 BURTC_CFG RW CONFIG Configuration Register 0x00C...
  • Page 386: Register Description

    Reference Manual BURTC - Back-Up Real Time Counter Offset Name Type Description 0x2024 BURTC_EM4WUEN_CLR EM4 wakeup request Enable Register 0x2028 BURTC_SYNCBUSY_CLR Synchronization Busy Register 0x202C BURTC_LOCK_CLR Configuration Lock Register 0x2030 BURTC_COMP_CLR RW LFSYNC Compare Value Register 0x3000 BURTC_IPVERSION_TGL IP version ID 0x3004 BURTC_EN_TGL RW ENABLE...
  • Page 387: Burtc_En - Module Enable Register

    Reference Manual BURTC - Back-Up Real Time Counter 16.5.2 BURTC_EN - Module Enable Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions BURTC Enable...
  • Page 388: Burtc_Cfg - Configuration Register

    Reference Manual BURTC - Back-Up Real Time Counter 16.5.3 BURTC_CFG - Configuration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CNTPRESC...
  • Page 389: Burtc_Cmd - Command Register

    Reference Manual BURTC - Back-Up Real Time Counter Name Reset Access Description ENABLE The top value of the BURTC is given by COMP DEBUGRUN Debug Mode Run Enable Set this bit to enable the BURTC to keep running in debug Value Mode Description...
  • Page 390: Burtc_Status - Status Register

    Reference Manual BURTC - Back-Up Real Time Counter 16.5.5 BURTC_STATUS - Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions LOCK...
  • Page 391: Burtc_Ien - Interrupt Enable Register

    Reference Manual BURTC - Back-Up Real Time Counter 16.5.7 BURTC_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions COMP...
  • Page 392: Burtc_Cnt - Counter Value Register

    Reference Manual BURTC - Back-Up Real Time Counter 16.5.9 BURTC_CNT - Counter Value Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:0 Counter Value Gives access to the counter value of the BURTC. Differs from SLOWLFRWSYNC behavior in that multiple writes cannot be queued up to same register while EN=0 16.5.10 BURTC_EM4WUEN - EM4 wakeup request Enable Register Offset...
  • Page 393: Burtc_Syncbusy - Synchronization Busy Register

    Reference Manual BURTC - Back-Up Real Time Counter 16.5.11 BURTC_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Sync busy for EN...
  • Page 394: Burtc_Lock - Configuration Lock Register

    Reference Manual BURTC - Back-Up Real Time Counter 16.5.12 BURTC_LOCK - Configuration Lock Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0...
  • Page 395: Buram - Backup Ram

    Reference Manual BURAM - Backup RAM 17. BURAM - Backup RAM Quick Facts What? The BURAM is a dedicated 128-byte low-power RAM that is retained in EM4. Why? Most of the system, including the RAM, is powered off at EM4 entry to minimize current draw. The pur- pose of the BURAM is to retain critical data for use when the system wakes up.
  • Page 396: Register Description

    Reference Manual BURAM - Backup RAM 17.4 Register Description 17.4.1 BURAM_RETx_REG - Retention Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 RETREG Latch based Retention register The RETREG registers are undefined out of reset. Any written RETREG values will be retained through any event other than a brownout or power-on reset.
  • Page 397: Letimer - Low Energy Timer

    Reference Manual LETIMER - Low Energy Timer 18. LETIMER - Low Energy Timer Quick Facts What? The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32768 Hz clock, the LETIMER is available in LETIMER EM0 Active, EM1 Sleep, EM2 DeepSleep, and EM3 Stop.
  • Page 398: Functional Description

    Reference Manual LETIMER - Low Energy Timer 18.3 Functional Description An overview of the LETIMER module is shown in Figure 18.1 LETIMER Overview on page 398. The LETIMER is a 24-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_TOP register can optionally act as a top value for the counter.
  • Page 399: Internal Overview

    Reference Manual LETIMER - Low Energy Timer 18.3.1 Internal Overview Timer The timer value can be read using the LETIMERn_CNT register. The value can be written, and it can also be cleared by setting the CLEAR command bit in LETIMERn_CMD. If the CLEAR and START commands are issued at the same time, the timer will be cleared, then start counting at the top value.
  • Page 400: Free Running Mode 4

    Reference Manual LETIMER - Low Energy Timer 18.3.2 Free Running Mode In free-running mode, the LETIMER acts as a regular timer and the repeat operation is disabled. When started, the timer runs until it is stopped using the STOP command bit in LETIMERn_CMD/PRS. A state machine for this mode is shown in Figure 18.2 LETIMER State Machine for Free-running Mode on page 400 Wait for positive clock edge...
  • Page 401: One-Shot Mode

    Reference Manual LETIMER - Low Energy Timer 18.3.3 One-shot Mode The one-shot repeat mode is the most basic repeat mode. In this mode, the repeat register LETIMERn_REP0 is decremented every time the timer underflows, and the timer stops when LETIMERn_REP0 goes from 1 to 0. In this mode, the timer counts down LETI- MERn_REP0 times, i.e.
  • Page 402: Buffered Mode

    Reference Manual LETIMER - Low Energy Timer 18.3.4 Buffered Mode The Buffered repeat mode allows buffered timer operation. When started, the timer runs LETIMERn_REP0 number of times. If LETI- MERn_REP1 has been written since the last time it was used and if it is nonzero, LETIMERn_REP1 is then loaded into LETI- MERn_REP0, and counting continues the new number of times.
  • Page 403: Double Mode

    Reference Manual LETIMER - Low Energy Timer 18.3.5 Double Mode The Double repeat mode works much like the one-shot repeat mode. The difference is that, where the one-shot mode counts as long as LETIMERn_REP0 is larger than 0, the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0.
  • Page 404: Clock Frequency

    Reference Manual LETIMER - Low Energy Timer 18.4 Clock Frequency The LETIMER clock source (EM23GRPACLK) is selected in the Clock Management Unit (CMU), and is typically configured to have a frequency of 32 kHz in EM0/1/2 and 1 kHz in EM3. The LETIMER clock prescaler is defined by LETIMERn_CTRL->CNTPRESC. The LETIMER Prescaled clock frequency is given by Figure 18.6 LETIMER Clock Frequency on page 404.
  • Page 405: Prs Input Triggers

    Reference Manual LETIMER - Low Energy Timer 18.5 PRS Input Triggers The LETIMER can be configured to start, stop, and/or clear based on PRS inputs. The diagram showing the functions of the PRS input triggers is shown in Figure 18.7 LETIMER PRS input triggers. on page 405.
  • Page 406: Output Action

    Reference Manual LETIMER - Low Energy Timer 18.7 Output Action For each of the Outputs, an output action can be set. The output actions can be set by configuring UFOA0 and UFOA1 in LETIMERn_CTRL. UFOA0 defines the action on output 0, while UFOA1 defines the action on output 1.
  • Page 407: Programmer's Model

    Reference Manual LETIMER - Low Energy Timer 18.12 Programmer's Model Important Note : Before writing any LFSYNC register, the module must be enabled ( LETIMER_EN->EN) and the LETIMER_SYN- CBUSY register should be polled to ensure the SYNC busy of that particular register field is not high. Write LETIMER Configuration into LETIMER_CTRL Register Enable clock to LETIMER module by setting LETIMER_EN->EN = 1 If used, write compare values into LETIMER_COMP0 and LETIMER_COMP1...
  • Page 408: Free Running Mode

    Reference Manual LETIMER - Low Energy Timer 18.12.1 FREE Running Mode LETIMER operation in Free running Mode with different output modes are shown in Figure 18.8 LETIMER - Free Running Mode Wave- form on page 408. In this example, REPMODE in LETIMERn_CTRL is set to FREE, CNTTOPEN also in LETIMERn_CTRL has been set and LETIMERn_TOP has been written to 3.
  • Page 409: One Shot Mode

    Reference Manual LETIMER - Low Energy Timer 18.12.2 One Shot Mode LETIMER operation in ONESHOT Mode with different output modes are shown in Figure 18.9 LETIMER - One Shot Mode Waveform on page 409. In this example, REPMODE in LETIMERn_CTRL is set to ONESHOT, CNTTOPEN also in LETIMERn_CTRL has been set and LETIMERn_TOP has been written to 3 and LETIMERn_REP0 has been written to 3.
  • Page 410: Buffered Mode

    Reference Manual LETIMER - Low Energy Timer 18.12.4 BUFFERED Mode In BUFFERED Mode LETIMERn_TOPBUFF and LETIMERn_REP1 registers are used as Buffers for LETIMERn_TOP and LETI- MERn_REP0 respectiverly. If both LETIMERn_TOP and LETIMERn_REP0 are 0 in buffered mode, and CNTTOPEN and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_TOPBUFF and LETIMERn_REP1 are loaded into LETIMERn_TOP and LETI- MERn_REP0 respectively when the timer is started.
  • Page 411: Continuous Output Generation

    Reference Manual LETIMER - Low Energy Timer 18.12.5 Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 18.8 LETIMER - Free Running Mode Waveform on page 408, but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous.
  • Page 412: Pwm Output

    Reference Manual LETIMER - Low Energy Timer Note: Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 18.12 LETIMER - Con- tinuous Operation on page 411 assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 18.13 LETIMERn_CNT Not Initialized to 0 on page 412shows an example where the LETIMER is started while LETI-...
  • Page 413: Register Map

    Reference Manual LETIMER - Low Energy Timer 18.13 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMER_IPVERSION IP version 0x004 LETIMER_EN RW ENABLE module en 0x008 LETIMER_CTRL Control Register 0x00C LETIMER_CMD W LFSYNC Command Register...
  • Page 414 Reference Manual LETIMER - Low Energy Timer Offset Name Type Description 0x200C LETIMER_CMD_CLR W LFSYNC Command Register 0x2010 LETIMER_STATUS_CLR Status Register 0x2018 LETIMER_CNT_CLR RWH LFSYNC Counter Value Register 0x201C LETIMER_COMP0_CLR Compare Value Register 0 0x2020 LETIMER_COMP1_CLR Compare Value Register 1 0x2024 LETIMER_TOP_CLR RWH LFSYNC...
  • Page 415: Register Description

    Reference Manual LETIMER - Low Energy Timer 18.14 Register Description 18.14.1 LETIMER_IPVERSION - IP version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 416: Letimer_Ctrl - Control Register

    Reference Manual LETIMER - Low Energy Timer 18.14.3 LETIMER_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16 CNTPRESC...
  • Page 417 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description ENABLE The top value of the LETIMER is given by COMP0 BUFTOP Buffered Top Set to load TOPBUFF into TOP when REP0 reaches 0 in BUFFERED mode, allowing a buffered top value. Value Mode Description...
  • Page 418: Letimer_Cmd - Command Register

    Reference Manual LETIMER - Low Energy Timer Name Reset Access Description BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around.
  • Page 419: Letimer_Status - Status Register

    Reference Manual LETIMER - Low Energy Timer 18.14.5 LETIMER_STATUS - Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RUNNING LETIMER Running...
  • Page 420: Letimer_Comp0 - Compare Value Register

    Reference Manual LETIMER - Low Energy Timer 18.14.7 LETIMER_COMP0 - Compare Value Register 0 Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:0...
  • Page 421: Letimer_Top - Counter Top Value Register

    Reference Manual LETIMER - Low Energy Timer 18.14.9 LETIMER_TOP - Counter TOP Value Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:0...
  • Page 422: Letimer_Rep0 - Repeat Counter Register 0

    Reference Manual LETIMER - Low Energy Timer 18.14.11 LETIMER_REP0 - Repeat Counter Register 0 Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions REP0...
  • Page 423: Letimer_If - Interrupt Flag Register

    Reference Manual LETIMER - Low Energy Timer 18.14.13 LETIMER_IF - Interrupt Flag Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions REP1...
  • Page 424: Letimer_Ien - Interrupt Enable Register

    Reference Manual LETIMER - Low Energy Timer 18.14.14 LETIMER_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions REP1...
  • Page 425: Letimer_Syncbusy - Synchronization Busy Register

    Reference Manual LETIMER - Low Energy Timer 18.14.15 LETIMER_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CTO1...
  • Page 426: Letimer_Prsmode - Prs Input Mode Select Register

    Reference Manual LETIMER - Low Energy Timer 18.14.16 LETIMER_PRSMODE - PRS Input mode select Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:26...
  • Page 427 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description FALLING Falling edge of selected PRS input can start the LETIMER BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 17:0 Reserved To ensure compatibility with future devices, always write bits to 0.
  • Page 428: Timer - Timer/Counter

    Reference Manual TIMER - Timer/Counter 19. TIMER - Timer/Counter Quick Facts What? The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms, and triggers timed actions in other peripherals. Why? Most applications have activities that need to be USART timed accurately with as little CPU intervention and energy consumption as possible.
  • Page 429: Features

    Reference Manual TIMER - Timer/Counter 19.2 Features • 16/32-bit auto reload up/down counter • Dedicated 16/32-bit reload register which serves as counter maximum • 3 or 4 Compare/Capture channels • Individually configurable as either input capture or output compare/PWM • Multiple Counter modes •...
  • Page 430: Functional Description

    Reference Manual TIMER - Timer/Counter • Dead-Time Insertion Unit • Complementary PWM outputs with programmable dead-time • Dead-time is specified independently for rising and falling edge • 10-bit prescaler • 6-bit time value • Outputs have configurable polarity • Outputs can be set inactive individually by software. •...
  • Page 431: Counter Modes

    Reference Manual TIMER - Timer/Counter 19.3.2 Counter Modes The timer consists of a counter that can be configured to the following modes, using the MODE field in TIMERn_CFG: • Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before counting up again. •...
  • Page 432 Reference Manual TIMER - Timer/Counter 19.3.2.2 Operation Figure 19.2 TIMER Hardware Timer/Counter Control on page 432 shows the hardware timer/counter control. Software can start or stop the counter by setting the START or STOP bits in TIMERn_CMD. The counter value (CNT in TIMERn_CNT) can always be written by software to any 16/32-bit value.
  • Page 433 Reference Manual TIMER - Timer/Counter 19.3.2.4 Peripheral Clock The peripheral clock for the timer (HFPERCLK ) clocks the logic for the timer block, even when it is not the selected clock source. TIMERn All TIMER instances in this device family use EM01GRPACLK selected in CMU_EM01GRPACLKCTRL_CLKSEL as their peripheral clock source (HFPERCLK TIMERn The peripheral clock to each timer can be used as a source with a configurable 10-bit prescaler.
  • Page 434 Reference Manual TIMER - Timer/Counter 19.3.2.8 Top Value Buffer The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB (buffer) register. When writing to the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event. Buffering ensures that the TOP value is not set below the actual count value.
  • Page 435 Reference Manual TIMER - Timer/Counter 19.3.2.9 Quadrature Decoder Quadrature decoding mode is used to track motion and determine both rotation direction and position. The quadrature decoder uses two input channels that are 90 degrees out of phase (see Figure 19.6 TIMER Quadrature Encoded Inputs on page 435).
  • Page 436 Reference Manual TIMER - Timer/Counter The quadrature decoder can be set in either X2 or X4 mode, which is configured in the QDM bit in TIMERn_CFG. See Figure 19.7 TIMER Quadrature Decoder Configuration on page 435 19.3.2.10 X2 Decoding Mode In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see Table 19.1 TIMER Counter Response in X2 Decoding Mode on page 436...
  • Page 437: Compare/Capture Channels

    Reference Manual TIMER - Timer/Counter 19.3.2.12 Rotational Position To calculate a position Figure 19.10 TIMER Rotational Position Equation on page 437 can be used. pos° = (CNT/X x N) x 360° Figure 19.10. TIMER Rotational Position Equation where X = Encoding type and N = Number of pulses per revolution. 19.3.3 Compare/Capture Channels The timer contains compare/capture channels, which can be independently configured in the following modes: 1.
  • Page 438 Reference Manual TIMER - Timer/Counter 19.3.3.3 Input Capture In input capture, the counter value (TIMERn_CNT) can be captured in the Input Capture Register (TIMERn_CCx_ICF) (see Figure 19.12 TIMER Input Capture on page 438). The CCPOL bits in TIMERn_STATUS indicate the polarity of the edge that triggered the capture in TIMERn_CCx_ICF.
  • Page 439 Reference Manual TIMER - Timer/Counter 19.3.3.4 Period/Pulse-Width Capture Period and/or pulse-width capture can only be possible with Channel 0 (CC0), because this is the only channel that can start and stop the timer. This can be done by setting the RISEA field in TIMERn_CTRL to Clear&Start, and selecting the desired input from either external pin or PRS, see Figure 19.13 TIMER Period and/or Pulse width Capture on page 439.
  • Page 440 Reference Manual TIMER - Timer/Counter 19.3.3.5 Compare Each compare/capture channel contains a comparator which outputs a compare match if the contents of TIMERn_CCx_OC matches the counter value, see Figure 19.14 TIMER Block Diagram Showing Comparison Functionality on page 440. In compare mode, each compare channel can be configured to either set, clear or toggle the output on an event (compare match, overflow or underflow).
  • Page 441 Reference Manual TIMER - Timer/Counter 19.3.3.6 Compare Mode Registers When running in output compare or PWM mode, the value in TIMERn_CCx_OC will be compared against the count value. In Compare mode the output can be configured to toggle, clear or set on compare match, overflow, and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL.
  • Page 442 Reference Manual TIMER - Timer/Counter 19.3.3.7 Frequency Generation (FRG) Frequency generation (see Figure 19.17 TIMER Up-count Frequency Generation on page 442) can be achieved in compare mode by: • Setting the counter in up-count mode • Enabling buffering of the TOP value. •...
  • Page 443 Reference Manual TIMER - Timer/Counter 19.3.3.9 Up-count (Single-slope) PWM If the counter is set to up-count and the compare/capture channel is put in PWM mode, single slope PWM output will be generated (see Figure 19.20 TIMER Up-count PWM Generation on page 443).
  • Page 444 Reference Manual TIMER - Timer/Counter 19.3.3.10 2x Count Mode (Up-count) When the timer is set in 2x mode, the TIMER will count up by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd OC value will generate a match on the closest lower even value as shown in Figure 19.25 TIMER CC out in 2x mode on page 444 Clock...
  • Page 445 Reference Manual TIMER - Timer/Counter 19.3.3.11 Up/Down-count (Dual-slope) PWM If the counter is set to up-down count and the compare/capture channel is put in PWM mode, dual slope PWM output will be generated Figure 19.29 TIMER Up/Down-count PWM Generation on page 445.The resolution (in bits) is given by Figure 19.30 TIMER Up/ Down-count PWM Resolution Equation on page...
  • Page 446 Reference Manual TIMER - Timer/Counter 19.3.3.12 2x Count Mode (Up/Down-count) When the timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd OC value will generate a match on the closest lower even value as shown in Figure 19.34 TIMER CC out in 2x mode on page 446 Clock...
  • Page 447 Reference Manual TIMER - Timer/Counter 19.3.3.14 Timer Configuration Lock To prevent software errors from making changes to the timer configuration, a configuration lock is available. Writing any value but 0xCE80 to LOCKKEY in TIMERn_LOCK will lock writes to TIMERn_CTRL, TIMERn_CFG, TIMERn_CMD, TIMERn_TOP, TIMERn_TOPB, TIMERn_CNT, TIMERn_CCx_CTRL, TIMERn_CCx_CFG, TIMERn_CCx_OC, and TIMERn_CCx_OCB.
  • Page 448: Dead-Time Insertion Unit

    Reference Manual TIMER - Timer/Counter 19.3.4 Dead-Time Insertion Unit Some timer modules include a Dead-Time Insertion unit suitable for motor control applications. Refer to the device data sheet to check which timer instances have this feature. The example settings in this section are for TIMER0, but identical settings can be used for other timers with DTI as well.
  • Page 449 Reference Manual TIMER - Timer/Counter DTFALLT DTRISET Select Original PWM (TIM0_CCx_pre) HFPERCLK Clock control Counter TIMERn Primary output (TIM0_CCx) Complementary Output (TIM0_CDTIx) Figure 19.41. TIMER Overview of Dead-Time Insertion Block for a Single PWM channel The DTI unit is enabled by setting DTEN in TIMER0_DTCFG. In addition to providing the complementary outputs, the DTI unit then also overrides the compare match outputs from the timer.
  • Page 450 Reference Manual TIMER - Timer/Counter Table 19.3. DTI Output When Timer Halted DTAR DTFATS State frozen safe running running 19.3.4.1 Output Polarity The value of the primary and complementary outputs in a pair will never be set active at the same time by the DTI unit. The polarity of the outputs can be changed if this is required by the application.
  • Page 451 Reference Manual TIMER - Timer/Counter 19.3.4.2 PRS Channel as a Source A PRS channel can be used as input to the DTI module instead of the PWM output from the timer for DTI channel 0. Setting DTPRSEN in TIMER0_DTCFG will override the source of the first DTI channel, driving TIM0_CC0 and TIM0_CDTI0, with the value on the PRS channel.
  • Page 452: Debug Mode

    Reference Manual TIMER - Timer/Counter 19.3.4.6 DTI Configuration Lock To prevent software errors from making changes to the DTI configuration, a configuration lock is available. Writing any value but 0xCE80 to LOCKKEY in TIMER0_DTLOCK locks writes to registers TIMER0_DTCFG, TIMER0_DTFCFG, TIMER0_DTCTRL, and TIMER0_DTTIMECFG.
  • Page 453: Register Map

    Reference Manual TIMER - Timer/Counter 19.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMER_IPVERSION IP version ID 0x004 TIMER_CFG RW CONFIG Configuration Register 0x008 TIMER_CTRL RW SYNC Control Register 0x00C TIMER_CMD W SYNC...
  • Page 454 Reference Manual TIMER - Timer/Counter Offset Name Type Description 0x1024 TIMER_CNT_SET RWH SYNC Counter Value Register 0x102C TIMER_LOCK_SET TIMER Configuration Lock Register 0x1030 TIMER_EN_SET RW ENABLE module en 0x1060 TIMER_CCx_CFG_SET RW CONFIG CC Channel Configuration Register 0x1064 TIMER_CCx_CTRL_SET RW SYNC CC Channel Control Register 0x1068 TIMER_CCx_OC_SET...
  • Page 455 Reference Manual TIMER - Timer/Counter Offset Name Type Description 0x20E8 TIMER_DTFCFG_CLR RW CONFIG DTI Fault Configuration Register 0x20EC TIMER_DTCTRL_CLR RW SYNC DTI Control Register 0x20F0 TIMER_DTOGEN_CLR RW SYNC DTI Output Generation Enable Register 0x20F4 TIMER_DTFAULT_CLR DTI Fault Register 0x20F8 TIMER_DTFAULTC_CLR W SYNC DTI Fault Clear Register 0x20FC TIMER_DTLOCK_CLR...
  • Page 456: Register Description

    Reference Manual TIMER - Timer/Counter 19.5 Register Description 19.5.1 TIMER_IPVERSION - IP version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 457: Timer_Cfg - Configuration Register

    Reference Manual TIMER - Timer/Counter 19.5.2 TIMER_CFG - Configuration Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:18 PRESC Prescaler Setting...
  • Page 458 Reference Manual TIMER - Timer/Counter Name Reset Access Description Value Mode Description Timer can start/stop/reload other timers with SYNC bit set Timer cannot start/stop/reload other timers with SYNC bit set RETIMEEN PWM output retimed enable Enable retiming of PWM output. Value Mode Description...
  • Page 459 Reference Manual TIMER - Timer/Counter Name Reset Access Description ENABLE Timer may be started, stopped and re-loaded from other timer instances. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions MODE Timer Mode These bits set the counting mode for the Timer.
  • Page 460: Timer_Ctrl - Control Register

    Reference Manual TIMER - Timer/Counter 19.5.3 TIMER_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions X2CNT 2x Count Mode Enable 2x count mode...
  • Page 461: Timer_Cmd - Command Register

    Reference Manual TIMER - Timer/Counter 19.5.4 TIMER_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions STOP Stop Timer Write a 1 to this bit to stop timer...
  • Page 462: Timer_Status - Status Register

    Reference Manual TIMER - Timer/Counter 19.5.5 TIMER_STATUS - Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CCPOL2 CCn Polarity In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC0_CCV.
  • Page 463 Reference Manual TIMER - Timer/Counter Name Reset Access Description ICFEMPTY1 Input capture fifo empty Set when input capture FIFO is empty ICFEMPTY0 Input capture fifo empty Set when input capture FIFO is empty 15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions OCBV2...
  • Page 464 Reference Manual TIMER - Timer/Counter Name Reset Access Description Counting up DOWN Counting down RUNNING Running Indicates if timer is running or not. silabs.com | Building a more connected world. Rev. 0.4 | 464...
  • Page 465: Timer_If - Interrupt Flag Register

    Reference Manual TIMER - Timer/Counter 19.5.6 TIMER_IF - Interrupt Flag Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions ICFUF2 Input capture FIFO underflow...
  • Page 466 Reference Manual TIMER - Timer/Counter Name Reset Access Description In INPUT CAPTURE mode this bit indicates that a new Capture event has taken place. In OUTPUTCOMPARE or PWM mode this bit indicates that a match event has taken place Capture Compare Channel 1 Interrupt Flag In INPUT CAPTURE mode this bit indicates that a new Capture event has taken place.
  • Page 467: Timer_Ien - Interrupt Enable Register

    Reference Manual TIMER - Timer/Counter 19.5.7 TIMER_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions ICFUF2 ICFUF2 Interrupt Enable...
  • Page 468: Timer_Top - Counter Top Value Register

    Reference Manual TIMER - Timer/Counter Name Reset Access Description Enable/Disable the CC1 interrupt CC0 Interrupt Enable Enable/Disable the CC0 interrupt Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DIRCHG Direction Change Detect Interrupt Enable Underflow Interrupt Enable Overflow Interrupt Enable 19.5.8 TIMER_TOP - Counter Top Value Register...
  • Page 469: Timer_Cnt - Counter Value Register

    Reference Manual TIMER - Timer/Counter 19.5.10 TIMER_CNT - Counter Value Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 Counter Value These bits hold the counter value. 19.5.11 TIMER_LOCK - TIMER Configuration Lock Register Offset Bit Position 0x02C Reset Access...
  • Page 470: Timer_En - Module En

    Reference Manual TIMER - Timer/Counter 19.5.12 TIMER_EN - module en Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Timer Module Enable The ENABLE bit enables the module.
  • Page 471: Timer_Ccx_Cfg - Cc Channel Configuration Register

    Reference Manual TIMER - Timer/Counter 19.5.13 TIMER_CCx_CFG - CC Channel Configuration Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions ICFWL Input Capture FIFO watermark level...
  • Page 472 Reference Manual TIMER - Timer/Counter Name Reset Access Description This bit is only used in Output Compare and PWM mode. When this bit is set in Compare or PWM mode,the output is set high when the counter is disabled. When counting resumes, this value will represent the initial value for the output. If the bit is cleared, the output will be cleared when the counter is disabled.
  • Page 473: Timer_Ccx_Ctrl - Cc Channel Control Register

    Reference Manual TIMER - Timer/Counter 19.5.14 TIMER_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:26 ICEVCTRL...
  • Page 474: Timer_Ccx_Oc - Oc Channel Value Register

    Reference Manual TIMER - Timer/Counter Name Reset Access Description 11:10 COFOA Counter Overflow Output Action Select output action on counter overflow. Value Mode Description NONE No action on counter overflow TOGGLE Toggle output on counter overflow CLEAR Clear output on counter overflow Set output on counter overflow CMOA Compare Match Output Action...
  • Page 475: Timer_Ccx_Ocb - Oc Channel Value Buffer Register

    Reference Manual TIMER - Timer/Counter 19.5.16 TIMER_CCx_OCB - OC Channel Value Buffer Register Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:0 Output Compare Value Buffer This field holds the Output Compare buffer value which will be written to TIMERn_CCx_OC on an update event if TIMERn_CCx_OCB contains valid data 19.5.17 TIMER_CCx_ICF - IC Channel Value Register Offset...
  • Page 476: Timer_Dtcfg - Dti Configuration Register

    Reference Manual TIMER - Timer/Counter 19.5.19 TIMER_DTCFG - DTI Configuration Register Offset Bit Position 0x0E0 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DTPRSEN DTI PRS Source Enable...
  • Page 477: Timer_Dttimecfg - Dti Time Configuration Register

    Reference Manual TIMER - Timer/Counter 19.5.20 TIMER_DTTIMECFG - DTI Time Configuration Register Offset Bit Position 0x0E4 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 21:16 DTFALLT...
  • Page 478: Timer_Dtfcfg - Dti Fault Configuration Register

    Reference Manual TIMER - Timer/Counter 19.5.21 TIMER_DTFCFG - DTI Fault Configuration Register Offset Bit Position 0x0E8 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DTEM23FEN DTI EM23 Fault Enable...
  • Page 479: Timer_Dtctrl - Dti Control Register

    Reference Manual TIMER - Timer/Counter 19.5.22 TIMER_DTCTRL - DTI Control Register Offset Bit Position 0x0EC Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DTIPOL DTI Inactive Polarity...
  • Page 480: Timer_Dtogen - Dti Output Generation Enable Register

    Reference Manual TIMER - Timer/Counter 19.5.23 TIMER_DTOGEN - DTI Output Generation Enable Register Offset Bit Position 0x0F0 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DTOGCDTI2EN...
  • Page 481: Timer_Dtfault - Dti Fault Register

    Reference Manual TIMER - Timer/Counter 19.5.24 TIMER_DTFAULT - DTI Fault Register Offset Bit Position 0x0F4 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DTEM23F DTI EM23 Entry Fault...
  • Page 482: Timer_Dtfaultc - Dti Fault Clear Register

    Reference Manual TIMER - Timer/Counter 19.5.25 TIMER_DTFAULTC - DTI Fault Clear Register Offset Bit Position 0x0F8 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DTEM23FC DTI EM23 Fault Clear...
  • Page 483: Timer_Dtlock - Dti Configuration Lock Register

    Reference Manual TIMER - Timer/Counter 19.5.26 TIMER_DTLOCK - DTI Configuration Lock Register Offset Bit Position 0x0FC Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0 DTILOCKKEY...
  • Page 484: Usart - Universal Synchronous Asynchronous Receiver/Transmitter

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20. USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? The USART handles high-speed UART, SPI-bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embed- ded systems and the USART allows efficient com- munication with a wide range of external devices.
  • Page 485: Features

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.2 Features • Asynchronous and synchronous (SPI) communication • Full duplex and half duplex • Separate TX/RX enable • Separate receive / transmit multiple entry buffers, with additional separate shift registers • Programmable baud rate, generated as an fractional division from the peripheral clock (PCLK USARTn •...
  • Page 486: Functional Description

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3 Functional Description An overview of the USART module is shown in Figure 20.1 USART Overview on page 486. This section describes all posible USART features. Please refer to the Device Datasheet to see what features a specific USART in- stance supports.
  • Page 487: Modes Of Operation

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.1 Modes of Operation The USART operates in either asynchronous or synchronous mode. In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the bus master, and both the master and slave sample and transmit data according to this clock.
  • Page 488 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.
  • Page 489 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL. When MSBF is cleared, data in a frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first. The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL.
  • Page 490 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.3 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Figure 20.3 USART Baud Rate on page 490.
  • Page 491 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USARTn_OVS =00 USARTn_OVS =01 Desired baud USARTn_CLKDIV/256 Actual baud rate USARTn_CLKDIV/256 Actual baud rate rate [baud/s] Error % Error % (to 32nd position) [baud/s] (to 32nd position) [baud/s] 57600 3,34375 57553,96 -0,080 7,6875 57553,96 -0,080...
  • Page 492 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.6 Transmit Buffer Operation The transmit-buffer is a multiple entry FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buf- fer, while using USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer.
  • Page 493 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.7 Frame Transmission Control The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of the written frame. The following options are available: • Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g.
  • Page 494 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.9 Receive Buffer Operation When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set.
  • Page 495 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.10 Blocking Incoming Data When using hardware frame recognition, as detailed in 20.3.2.20 Multi-Processor Mode 20.3.2.21 Collision Detection, it is necessa- ry to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer. This is accomplished by blocking incoming data.
  • Page 496 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.11 Clock Recovery and Filtering The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors. When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame.
  • Page 497 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/1 Figure 20.8. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices.
  • Page 498 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.14 Local Loopback The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default. This is not the only option howev- er. When LOOPBK in USARTn_CTRL is set, the receiver is connected to the U(S)n_TX pin as shown in Figure 20.9 USART Local Loopback on page 498.
  • Page 499 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.17 Single Data-link with External Driver Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of tristating the transmitter when receiving data, the external driver must be disabled. This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART.
  • Page 500 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.19 Large Frames As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when working with USART-frames of 10 or more data bits. To transmit such a frame, at least two elements must be available in the transmit buffer.
  • Page 501 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two buffer elements. If BYTESWAP is cleared, the least significant 8 bits of the received frame are loaded into the first element of the receive buffer, and the remaining bits are loaded into the second element, as shown in Figure 20.13 USART Reception of Large Frames on page...
  • Page 502 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.22 SmartCard Mode In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stop-bits (guard time), the 7816 data frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard time to indicate a parity error.
  • Page 503: Synchronous Operation

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 1/2 stop bit NAK or stop Stop 13 14 15 16 1 9 10 11 14 15 16 17 18 X Figure 20.16. USART SmartCard Stop Bit Sampling For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one of the timers.
  • Page 504 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.2 Clock Generation The bit-rate in synchronous mode is given by Figure 20.17 USART Synchronous Mode Bit Rate on page 504. As in the case of asyn- chronous operation, the clock division factor have a 15-bit integral part and a 5-bit fractional part. br = f /(2 x (1 + USARTn_CLKDIV/256)) PCLK...
  • Page 505 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL and TXC are updated on the first setup clock edge of the succeeding frame, or when CS is deasserted. 20.3.3.3 Master Mode When in master mode, the USART is in full control of the data flow on the synchronous bus.
  • Page 506 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.7 Synchronous Half Duplex Communication Half duplex communication in synchronous mode is very similar to half duplex communication in asynchronous mode as detailed in 20.3.2.15 Asynchronous Half Duplex Communication. The main difference is that in this mode, the master must generate the bus clock even when it is not transmitting data, i.e.
  • Page 507 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.10 Major Modes The USART supports a set of different I2S formats as shown in Table 20.9 USART I2S Modes on page 507, but it is not limited to these modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO enables mono mode, i.e.
  • Page 508 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USn_CLK USn_CS (word select) USn_TX/ USn_RX Right channel Left channel Right channel Figure 20.22. USART Left-justified I2S waveform A right-justified stream is shown in Figure 20.23 USART Right-justified I2S waveform on page 508.
  • Page 509: Hardware Flow Control

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.11 Using I2S Mode When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits. 8 databits can be used in all modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared.
  • Page 510: Prs Clk Input

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.8 PRS CLK Input The USART can be configured to receive clock directly from a PRS channel by setting CLKPRSEN in USARTn_CTRLX. The PRS channel used is selected using PRSSEL in PRS_USARTn_CLK. This is useful in synchronous slave mode and can together with RX PRS input be used to input data from PRS.
  • Page 511: Timer

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10 Timer In addition to the TX sequence timer, there is a versatile 8 bit timer that can generate up to three event pulses. These pulses can be used to create timing for a variety of uses such as RX timeout, break detection, response timeout, and RX enable delay. Transmission delay, CS setup, inter-character spacing, and CS hold use the TX sequence counter.
  • Page 512 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter TIMECMP2 TIMECMP1 TIMECMP0 TCMPn TXST RXACT TCMPVALn RXACTN TSTOP GP_CNT[7:0] clear DISABLE TCMP TXEOF Compare TCMPn enable RXACT RXEOF TSTART START_An RESTARTEN START_Bn START_A2 START_B2 START_A1 start START_B1 event START_A0 8 bit bit time GP_CNT[7:0] START_B0...
  • Page 513 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Application TSTARTn TSTOPn TCMPVALn Other Break Detect TSTART1 = RXACT TSTOP1 = TCMPVAL1 TCMP1 in USARTn_IEN RXACTN = 0x0C TX delayed start of transmission and TSTART0 = DISA- TSTOP0 = TCMP0, TCMPVAL0 TXDELAY = TCMP0, CSSETUP = CS setup BLE, TSTART1 =...
  • Page 514 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10.2 RX Timeout A receiver timeout function can be implemented by using the RX end of frame to start comparator 1 and look for the RX start bit RXACT to disable the comparator. See Table 20.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 512 for details on setting up this example.
  • Page 515 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10.4 TX Start Delay Some applications may require a delay before the start of transmission. This example in Figure 20.29 USART TXSEQ Timing on page shows the TXSEQ timer used to delay the start of transmission by 4 baud times before the start of CS, and by 2 baud times with CS asserted.
  • Page 516: Interrupts

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10.8 Combined TX and RX Example This example describes how to alternate between TX and RX frames. This has a 28 baud-time space after RX and a 16 baud-time space after TX. The TSTART1 in USARTn_TIMECMP1 is set to RXEOF which uses the the receiver end of frame to start the timer. The TSTOP1 is set to TCMP1 to generate an event after 28 baud times.
  • Page 517: Irda Modulator/ Demodulator

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.12 IrDA Modulator/ Demodulator The IrDA modulator implements the physical layer of the IrDA specification, which is necessary for communication over IrDA. The mod- ulator takes the signal output from the USART module, and modulates it before it leaves the USART. In the same way, the input signal is demodulated before it enters the actual USART module.
  • Page 518: Register Map

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USART_IPVERSION IPVERSION 0x004 USART_EN USART Enable 0x008 USART_CTRL Control Register 0x00C USART_FRAME USART Frame Format Register 0x010 USART_TRIGCTRL USART Trigger Control register...
  • Page 519 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Offset Name Type Description 0x1020 USART_RXDATAX_SET RX Buffer Data Extended Register 0x1024 USART_RXDATA_SET RX Buffer Data Register 0x1028 USART_RXDOUBLEX_SET RX Buffer Double Data Extended Register 0x102C USART_RXDOUBLE_SET RX FIFO Double Data Register 0x1030 USART_RXDATAXP_SET RX Buffer Data Extended Peek Register...
  • Page 520 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Offset Name Type Description 0x2048 USART_IF_CLR RWH INTFLAG Interrupt Flag Register 0x204C USART_IEN_CLR Interrupt Enable Register 0x2050 USART_IRCTRL_CLR IrDA Control Register 0x2054 USART_I2SCTRL_CLR I2S Control Register 0x2058 USART_TIMING_CLR Timing Register 0x205C USART_CTRLX_CLR Control Register Extended 0x2060 USART_TIMECMP0_CLR...
  • Page 521: Register Description

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5 Register Description 20.5.1 USART_IPVERSION - IPVERSION Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 522: Usart_Ctrl - Control Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.3 USART_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description SMSDELAY Synchronous Master Sample Delay Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher speeds MVDIS Majority Vote Disable...
  • Page 523 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description ERRSDMA Halt DMA On Error When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only). Value Mode Description DISABLE Framing and parity errors have no effect on DMA requests from the USART ENABLE DMA requests from the USART are blocked while the PERR or...
  • Page 524 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXINV Receiver Input Invert Setting this bit will invert the input to the USART receiver. Value Mode Description DISABLE Input is passed directly to the receiver ENABLE Input is inverted before it is passed to the receiver TXBIL TX Buffer Interrupt Level Determines the interrupt and status level of the transmit buffer.
  • Page 525 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description IDLEHIGH The bus clock used in synchronous mode has a high base value Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Oversampling...
  • Page 526 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description DISABLE The USART operates in asynchronous mode ENABLE The USART operates in synchronous mode silabs.com | Building a more connected world. Rev. 0.4 | 526...
  • Page 527: Usart_Frame - Usart Frame Format Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.4 USART_FRAME - USART Frame Format Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 13:12...
  • Page 528 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Each frame contains 6 data bits SEVEN Each frame contains 7 data bits EIGHT Each frame contains 8 data bits NINE Each frame contains 9 data bits Each frame contains 10 data bits ELEVEN Each frame contains 11 data bits TWELVE...
  • Page 529: Usart_Trigctrl - Usart Trigger Control Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.5 USART_TRIGCTRL - USART Trigger Control register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RXATX2EN...
  • Page 530: Usart_Cmd - Command Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.6 USART_CMD - Command Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLEARRX...
  • Page 531: Usart_Status - Usart Status Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.7 USART_STATUS - USART Status Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 17:16...
  • Page 532: Usart_Clkdiv - Clock Control Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Indicates the level of the transmit buffer. If TXBIL is 0x0, TXBL is set whenever the transmit buffer is completely empty. Otherwise TXBL is set whenever the TX Buffer becomes half full. TX Complete Set when a transmission has completed and no more data is available in the transmit buffer and shift register.
  • Page 533: Usart_Rxdatax - Rx Buffer Data Extended Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.9 USART_RXDATAX - RX Buffer Data Extended Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions FERR...
  • Page 534: Usart_Rxdoublex - Rx Buffer Double Data Extended Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.11 USART_RXDOUBLEX - RX Buffer Double Data Extended Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description FERR1 Data Framing Error 1 Set if data in buffer has a framing error. Can be the result of a break condition. PERR1 Data Parity Error 1 Set if data in buffer has a parity error (asynchronous mode only).
  • Page 535: Usart_Rxdouble - Rx Fifo Double Data Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.12 USART_RXDOUBLE - RX FIFO Double Data Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:8...
  • Page 536: Usart_Rxdoublexp - Rx Buffer Double Data Extended Peek R

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.14 USART_RXDOUBLEXP - RX Buffer Double Data Extended Peek R... Offset Bit Position 0x034 Reset Access Name Name Reset Access Description FERRP1 Data Framing Error 1 Peek Set if data in buffer has a framing error. Can be the result of a break condition. PERRP1 Data Parity Error 1 Peek Set if data in buffer has a parity error (asynchronous mode only).
  • Page 537: Usart_Txdatax - Tx Buffer Data Extended Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.15 USART_TXDATAX - TX Buffer Data Extended Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RXENAT...
  • Page 538: Usart_Txdata - Tx Buffer Data Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.16 USART_TXDATA - TX Buffer Data Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TXDATA...
  • Page 539: Usart_Txdoublex - Tx Buffer Double Data Extended Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.17 USART_TXDOUBLEX - TX Buffer Double Data Extended Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description RXENAT1 Enable RX After Transmission Set to enable reception after transmission. TXDISAT1 Clear TXEN After Transmission Set to disable transmitter and release data bus directly after transmission.
  • Page 540: Usart_Txdouble - Tx Buffer Double Data Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.18 USART_TXDOUBLE - TX Buffer Double Data Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:8...
  • Page 541: Usart_If - Interrupt Flag Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.19 USART_IF - Interrupt Flag Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TCMP2...
  • Page 542 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RX Buffer Full Interrupt Flag Set when the receive buffer becomes full. RXDATAV RX Data Valid Interrupt Flag Set when data becomes available in the receive buffer. TXBL TX Buffer Level Interrupt Flag Set when buffer becomes empty if buffer level is set to 0x0, or when the number of empty TX buffer elements equals...
  • Page 543: Usart_Ien - Interrupt Enable Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.20 USART_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TCMP2...
  • Page 544 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RX Buffer Full Interrupt Enable Set when the receive buffer becomes full. RXDATAV RX Data Valid Interrupt Enable Set when data becomes available in the receive buffer. TXBL TX Buffer Level Interrupt Enable Set when buffer becomes empty if buffer level is set to 0x0, or when the number of empty TX buffer elements equals...
  • Page 545: Usart_Irctrl - Irda Control Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.21 USART_IRCTRL - IrDA Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions IRPRSEN...
  • Page 546: Usart_I2Sctrl - I2S Control Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.22 USART_I2SCTRL - I2S Control Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 10:8...
  • Page 547 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Set the U(S)ART in I2S mode. silabs.com | Building a more connected world. Rev. 0.4 | 547...
  • Page 548: Usart_Timing - Timing Register

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.23 USART_TIMING - Timing Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 30:28 CSHOLD...
  • Page 549 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 22:20...
  • Page 550: Usart_Ctrlx - Control Register Extended

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.24 USART_CTRLX - Control Register Extended Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLKPRSEN...
  • Page 551 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Value Mode Description DISABLE Continue to transmit until TX buffer is empty ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock;...
  • Page 552: Usart_Timecmp0 - Used To Generate Interrupts And Vario

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.25 USART_TIMECMP0 - Used to generate interrupts and vario... Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RESTARTEN...
  • Page 553 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXEOF Comparator 0 and timer are started at RX end of frame 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TCMPVAL...
  • Page 554: Usart_Timecmp1 - Used To Generate Interrupts And Vario

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.26 USART_TIMECMP1 - Used to generate interrupts and vario... Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RESTARTEN...
  • Page 555 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXEOF Comparator 1 and timer are started at RX end of frame 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TCMPVAL...
  • Page 556: Usart_Timecmp2 - Used To Generate Interrupts And Vario

    Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.27 USART_TIMECMP2 - Used to generate interrupts and vario... Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions RESTARTEN...
  • Page 557 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXEOF Comparator 2 and timer are started at RX end of frame 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TCMPVAL...
  • Page 558: I2C - Inter-Integrated Circuit Interface

    Reference Manual I2C - Inter-Integrated Circuit Interface 21. I2C - Inter-Integrated Circuit Interface Quick Facts What? The I C interface allows communication on I buses with the lowest energy consumption possible. Why? C is a popular serial bus that enables communica- tion with a number of external devices using only Gecko Device C master/slave...
  • Page 559: Functional Description

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3 Functional Description An overview of the I2C module is shown in Figure 21.1 I2C Overview on page 559. Peripheral Bus C Control and Transmit Buffer Receive Buffer Status (2-level FIFO) (2-level FIFO) I2Cn_SDA Symbol Transmit...
  • Page 560: I2C-Bus Overview

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.1 I2C-Bus Overview The I C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in Figure 21.2 I2C-Bus Example on page 560. As a true multi-master bus it includes collision detection and arbitration to resolve situations where multiple masters transmit data at the same time without data loss.
  • Page 561 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus. All transactions on the bus begin with a START condition (S) and end with a STOP condition (P). As shown in Figure 21.4 I2C START and STOP Conditions on page 561, a START condition is generated by pulling the SDA line low while SCL is high, and a STOP condition is generated by pulling the SDA line high...
  • Page 562 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.1.2 Bus Transfer When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The master then transmits the address of the slave it wishes to interact with and a single R/W bit telling whether it wishes to read from the slave (R/W bit set to 1) or write to the slave (R/W bit set to 0).
  • Page 563 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.1.3 Addresses C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains the address of the slave that the master wants to contact. In the 7-bit address space, several addresses are reserved. These addresses are summarized in Table 21.1 I2C Reserved I C Addresses on page...
  • Page 564: Enable And Reset

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.1.5 Arbitration, Clock Synchronization, Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration occurs when two devices try to drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain bus configuration.
  • Page 565: Clock Generation

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.5 Clock Generation The I C peripheral clock (I2CCLK) for I2C0 is derived from the LSPCLK (max freq = 25 MHz), and for I2C1 is derived from the PCLK (max freq = 50 MHz). The SCL signal generated by the I C master determines the maximum transmission rate on the bus.
  • Page 566 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.7.1 Transmit Buffer and Shift Register The I C transmitter has a 2-level FIFO transmit buffer and a transmit shift register as shown in Figure 21.1 I2C Overview on page 559. A byte is loaded into the transmit buffer by writing to I2C_TXDATA or 2 bytes can be loaded simultaneously in the transmit buffer by writing to I2C_TXDOUBLE.
  • Page 567 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.7.2 Receive Buffer and Shift Register The I C receiver uses a 2-level FIFO receive buffer and a receive shift register as shown in Figure 21.14 I2C Receive Buffer Operation on page 567. When a byte has been fully received by the receive shift register, it is loaded into the receive buffer if there is room for it, making the shift register empty to receive another byte.
  • Page 568: Master Operation

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.8 Master Operation A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2C_CMD. The command schedules a START condition, and makes the I C module generate a start condition whenever the bus becomes free.
  • Page 569: Bus States

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.8.1 Master State Machine The master state machine is shown in Figure 21.15 I2C Master State Machine on page 569. A master operation starts in the far left of the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when arriving at the right side of the state machine.
  • Page 570 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.8.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2C_IF is set. The action(s) required by software depends on the current state the of the I C module.
  • Page 571 Reference Manual I2C - Inter-Integrated Circuit Interface When several interactions are possible from a set of pending commands, the interaction with the highest priority, i.e., the interaction closest to the top of Table 21.2 I2C Interactions in Prioritized Order on page 570 is applied to the bus.
  • Page 572 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.8.5 Master Transmitter To transmit data to a slave, the master must operate as a master transmitter. Table 21.3 I2C Master Transmitter on page 572 shows the states the I C module goes through while acting as a master transmitter. Every state where an interaction is required has the possi- ble interactions listed, along with the result of the interactions.
  • Page 573 Reference Manual I2C - Inter-Integrated Circuit Interface I2C_STATE Description I2C_IF Required in- Response teraction 0x97 ADDR+W transmitted, ACK interrupt flag TXDATA DATA will be sent ACK received (BUSHOLD interrupt STOP STOP will be sent. Bus will be released flag) START Repeated start condition will be sent STOP + STOP will be sent and the bus released.
  • Page 574 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.8.6 Master Receiver To receive data from a slave, the master must operate as a master receiver, see Table 21.4 I2C Master Receiver on page 574. This is done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a master transmitter. The address byte loaded into the data register thus has to contain the 7-bit slave address in the 7 most significant bits of the byte, and have the least significant bit set.
  • Page 575 Reference Manual I2C - Inter-Integrated Circuit Interface I2C_STATE Description I2C_IF Required in- Response teraction 0xB3 Data received RXDATA interrupt ACK + RXDA- ACK will be transmitted, reception continues flag(BUSHOLD inter- rupt flag) NACK + NACK will be transmitted, reception continues CONT + RXDATA ACK/NACK +...
  • Page 576: Slave Operation

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.9 Bus States The I2C_STATE register can be used to determine which state the I C module and the I C bus are in at a given time. The register consists of the STATE bit-field, which shows which state the I C module is at in any ongoing transmission, and a set of single-bits, which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I C module waiting for a soft-...
  • Page 577 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.10.1 Slave State Machine The slave state machine is shown in Figure 21.16 I2C Slave State Machine on page 577. The dotted lines show where I C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission pro- ceed.
  • Page 578 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.10.3 Slave Transmitter When SLAVE in I2C_CTRL is set, the RSTART interrupt flag in I2C_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit. If there is no room in the receive shift register for the address, the bus will be held by the slave until room is available in the shift register.
  • Page 579 Reference Manual I2C - Inter-Integrated Circuit Interface I2C_STATE Description I2C_IF Required in- Response teraction Stop received SSTOP interrupt flag None The slave goes idle START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt flag None The slave goes idle START START will be sent when the bus becomes idle silabs.com | Building a more connected world.
  • Page 580: Transfer Automation

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.10.4 Slave Receiver A slave receiver operation is started in the same way as a slave transmitter operation, with the exception that the address transmitted by the master has the R/W bit cleared (W), indicating that the master wishes to write to the slave. The slave then goes into slave receiv- er mode.
  • Page 581: Using 10-Bit Addresses

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.11.1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, soft- ware is thus relieved of moving data to and from memory after each transferred byte. 21.3.11.2 Automatic ACK When AUTOACK in I2C_CTRL is set, an ACK is sent automatically whenever an ACK interaction is possible and no higher priority interactions are pending.
  • Page 582 Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.13.2 Bus Reset A bus reset can be performed by setting the START and STOP commands in I2C_CMD while the transmit buffer is empty. A START condition will then be transmitted, immediately followed by a STOP condition. A bus reset can also be performed by transmitting a START command with the transmit buffer empty and AUTOSE set.
  • Page 583: Dma Support

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.3.13.7 Clock Low Error The I C module can continue transmission in parallel with another device for the entire transaction, as long as the two communications are identical. A case may arise when (before an arbitration has been decided upon) the I C module decides to send out a repeated START or a STOP condition while the other device is still sending data.
  • Page 584: Register Map

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2C_IPVERSION IP VERSION Register 0x004 I2C_EN Enable Register 0x008 I2C_CTRL Control Register 0x00C I2C_CMD Command Register 0x010 I2C_STATE...
  • Page 585 Reference Manual I2C - Inter-Integrated Circuit Interface Offset Name Type Description 0x2004 I2C_EN_CLR Enable Register 0x2008 I2C_CTRL_CLR Control Register 0x200C I2C_CMD_CLR Command Register 0x2010 I2C_STATE_CLR State Register 0x2014 I2C_STATUS_CLR Status Register 0x2018 I2C_CLKDIV_CLR Clock Division Register 0x201C I2C_SADDR_CLR Slave Address Register 0x2020 I2C_SADDRMASK_CLR Slave Address Mask Register...
  • Page 586: Register Description

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5 Register Description 21.5.1 I2C_IPVERSION - IP VERSION Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP version The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 587: I2C_Ctrl - Control Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.3 I2C_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SDAMONEN SDA Monitor Enable...
  • Page 588 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. GIBITO Go Idle on Bus Idle Timeout When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated. Value Mode Description...
  • Page 589 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description HALF_FULL TXBL status and the TXBL interrupt flag are set when the trans- mit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full GCAMEN General Call Address Match Enable Set to enable address match on general call in addition to the programmed slave address.
  • Page 590 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set this bit to allow the device to be selected as an I2C slave. Value Mode Description DISABLE All addresses will be responded to with a NACK ENABLE Addresses matching the programmed slave address or the gen- eral call address (if enabled) require a response from software.
  • Page 591: I2C_Cmd - Command Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.4 I2C_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLEARPC Clear Pending Commands...
  • Page 592: I2C_State - State Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.5 I2C_STATE - State Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions STATE Transmission State...
  • Page 593: I2C_Status - Status Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.6 I2C_STATUS - Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 11:10 TXBUFCNT...
  • Page 594: I2C_Clkdiv - Clock Division Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.7 I2C_CLKDIV - Clock Division Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Clock Divider...
  • Page 595: I2C_Saddrmask - Slave Address Mask Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.9 I2C_SADDRMASK - Slave Address Mask Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SADDRMASK...
  • Page 596: I2C_Rxdouble - Receive Buffer Double Data Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.11 I2C_RXDOUBLE - Receive Buffer Double Data Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:8...
  • Page 597: I2C_Rxdoublep - Receive Buffer Double Data Peek Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.13 I2C_RXDOUBLEP - Receive Buffer Double Data Peek Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:8...
  • Page 598: I2C_Txdouble - Transmit Buffer Double Data Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.15 I2C_TXDOUBLE - Transmit Buffer Double Data Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:8...
  • Page 599: I2C_If - Interrupt Flag Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.16 I2C_IF - Interrupt Flag Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SDAERR...
  • Page 600 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP condition, then the MSTOP interrupt flag is not set. NACK Not Acknowledge Received Interrupt Flag Set when a NACK has been received.
  • Page 601: I2C_Ien - Interrupt Enable Register

    Reference Manual I2C - Inter-Integrated Circuit Interface 21.5.17 I2C_IEN - Interrupt Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SDAERR...
  • Page 602 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP condition, then the MSTOP interrupt flag is not set. NACK Not Acknowledge Received Interrupt Flag Set when a NACK has been received.
  • Page 603: Acmp - Analog Comparator

    Reference Manual ACMP - Analog Comparator 22. ACMP - Analog Comparator Quick Facts What? The ACMP (Analog Comparator) compares two ana- log signals and returns a digital value telling which is greater. Why? Applications often do not need to know the exact value of an analog signal, only if it has passed a cer- tain threshold.
  • Page 604: Functional Description

    Reference Manual ACMP - Analog Comparator 22.3 Functional Description An overview of the ACMP is shown in Figure 22.1 ACMP Overview on page 604. POSSEL Ground ACMPRDY Analog Bus A (even) Analog Bus B (even) Analog Bus CD (even) GPIO CSRESSEL Analog Bus A (odd) Analog Bus B (odd)
  • Page 605: Warmup Time

    Reference Manual ACMP - Analog Comparator 22.3.2 Warmup Time When the comparator is enabled or the input muxes are reconfigured, it requires some time to stabilize. On first enable (ACMP_EN_EN = 1), the comparator core requires 2.5 us to stabilize. In addition to this, any references selected may require some time to warm up. See table Table 22.1 Warmup Time on page 605 for warmup times for the different references.
  • Page 606: Vrefdiv Sources

    Reference Manual ACMP - Analog Comparator 22.3.5 VREFDIV Sources The ACMP has two internal bandgap references: 2.5 V and 1.25 V. In addition, AVDD can be used as a reference. To select one of these references, configure POSSEL / NEGSEL to VREFDIVAVDD, VREFDIV1V25, or VREFDIV2V5. The ACMP also includes sam- ple/hold functionality to reduce energy consumption.
  • Page 607: Capacitive Sense Mode

    Reference Manual ACMP - Analog Comparator 22.3.8 Capacitive Sense Mode The analog comparator includes specialized hardware for capacitive sensing of passive push buttons. Such buttons are traces on the PCB laid out in a way that creates a parasitic capacitor between the button and the ground node. Because a human finger will have a small intrinsic capacitance to ground, the capacitance of the button will increase when the button is touched.
  • Page 608: Interrupts And Prs Output

    Reference Manual ACMP - Analog Comparator 22.3.9 Interrupts and PRS Output The analog comparator includes independent output flags for rising edge (RISEIF) and falling edge (FALLIF) events. These will be set when a rising or falling edge is detected, respectively. Three other interrupt sources are also available.
  • Page 609: Register Map

    Reference Manual ACMP - Analog Comparator 22.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ACMP_IPVERSION IP version ID 0x004 ACMP_EN RW ENABLE ACMP enable 0x008 ACMP_CFG RW CONFIG Configuration register 0x00C ACMP_CTRL Control Register...
  • Page 610: Register Description

    Reference Manual ACMP - Analog Comparator Offset Name Type Description 0x3020 ACMP_SYNCBUSY_TGL Syncbusy 22.5 Register Description 22.5.1 ACMP_IPVERSION - IP version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 611: Acmp_Cfg - Configuration Register

    Reference Manual ACMP - Analog Comparator 22.5.3 ACMP_CFG - Configuration register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions ACCURACY ACMP accuracy mode...
  • Page 612: Acmp_Ctrl - Control Register

    Reference Manual ACMP - Analog Comparator Name Reset Access Description POS30MV 30mV hysteresis on positive edge transitions NEG10MV 10mV hysteresis on negative edge transitions NEG20MV 20mV hysteresis on negative edge transitions NEG30MV 30mV hysteresis on negative edge transitions Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions BIAS...
  • Page 613: Acmp_Inputctrl - Input Control Register

    Reference Manual ACMP - Analog Comparator 22.5.5 ACMP_INPUTCTRL - Input Control Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 30:28 CSRESSEL...
  • Page 614 Reference Manual ACMP - Analog Comparator Name Reset Access Description VSENSE01DIV4LP Low-power VSENSE0 divided by 4 VSENSE11DIV4 VSENSE1 divided by 4 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 CAPSENSE Capsense mode Port A, Pin0 Port A, Pin1 Port A, Pin2 Port A, Pin3 Port A, Pin4 Port A, Pin5 Port A, Pin6...
  • Page 615 Reference Manual ACMP - Analog Comparator Name Reset Access Description Port C, Pin1 Port C, Pin2 Port C, Pin3 Port C, Pin4 Port C, Pin5 Port C, Pin6 Port C, Pin7 Port C, Pin8 Port C, Pin9 PC10 Port C, Pin10 PC11 Port C, Pin11 PC12...
  • Page 616 Reference Manual ACMP - Analog Comparator Name Reset Access Description VREFDIVAVDDLP Low-Power Divided AVDD VREFDIV1V25 Divided 1V25 reference VREFDIV1V25LP Low-power Divided 1V25 reference VREFDIV2V5 Divided 2V5 reference VREFDIV2V5LP Low-power Divided 2V5 reference VSENSE01DIV4 VSENSE0 divided by 4 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 VSENSE11DIV4 VSENSE1 divided by 4 VSENSE11DIV4LP...
  • Page 617 Reference Manual ACMP - Analog Comparator Name Reset Access Description PB12 Port B, Pin12 PB13 Port B, Pin13 PB14 Port B, Pin14 PB15 Port B, Pin15 Port C, Pin0 Port C, Pin1 Port C, Pin2 Port C, Pin3 Port C, Pin4 Port C, Pin5 Port C, Pin6 Port C, Pin7...
  • Page 618: Acmp_Status - Status Register

    Reference Manual ACMP - Analog Comparator 22.5.6 ACMP_STATUS - Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PORTALLOCERR Port allocation error...
  • Page 619: Acmp_If - Interrupt Flag Register

    Reference Manual ACMP - Analog Comparator 22.5.7 ACMP_IF - Interrupt Flag Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PORTALLOCERR Port allocation error...
  • Page 620: Acmp_Ien - Interrupt Enable Register

    Reference Manual ACMP - Analog Comparator 22.5.8 ACMP_IEN - Interrupt Enable Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PORTALLOCERR Port allocation error interrupt enable...
  • Page 621: Iadc - Incremental Analog To Digital Converter

    Reference Manual IADC - Incremental Analog to Digital Converter 23. IADC - Incremental Analog to Digital Converter Quick Facts What? The IADC is used to convert analog voltages into a digital representation and features high-speed, low- power operation. Why? In many applications there is a need to measure an- alog signals and record them in a digital representa- tion, without exhausting the energy source.
  • Page 622: Features

    Reference Manual IADC - Incremental Analog to Digital Converter 23.2 Features • Flexible oversampled architecture allows for tradeoffs between speed and resolution. • 1 Msps with oversampling ratio = 2 • 555 ksps with oversampling ratio = 4 • Internal and external conversion trigger sources •...
  • Page 623: Functional Description

    Reference Manual IADC - Incremental Analog to Digital Converter • Available interrupt sources: • Single FIFO has DVL (data valid level) entries available (also generates DMA request) • Scan FIFO has DVL (data valid level) entries available (also generates DMA request) •...
  • Page 624: Register Access

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.1 Register Access Many of the IADC module's configuration registers can only be written while the module is disabled (IADC_EN_EN = 0). These are IADC_CTRL, IADC_TIMER, IADC_CMPTHR, IADC_TRIGGER, IADC_CFGx, IADC_SCALEx, IADC_SCHEDx, and IADC_SCANx. A typical setup sequence for the IADC module is: 1.
  • Page 625: Clocking

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.2 Clocking The IADC logic is partitioned into two clock domains: CLK_BUS (ABPIF) and CLK_SRC_ADC (CORE). The APBIF domain contains the IADC registers and FIFO read logic. The rest of the IADC is clocked mainly by CLK_SRC_ADC and ADC_CLK, both of which are de- rived from CLK_CMU_ADC, as shown in Figure 23.2 Clocking on page 625.
  • Page 626: Conversion Timing

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3 Conversion Timing The IADC takes multiple samples of the analog signal to produce each output. The number of input samples contributing to an output word is determined by the oversampling ratio (OSR). Higher OSR settings will improve the ADC's INL and DNL, and reduce system- level noise, but require more time for each conversion.
  • Page 627 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3.2 Conversion Pipeline The IADC uses a pipelined architecture to perform different stages of the ADC conversion in parallel. The conversion time for a single sample can be determined from the OSR and the pre-scaled CLK_ADC frequency (f ) as: CLK_ADC Conversion Time = ((4 * OSR) + 2) / f...
  • Page 628 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3.3 Scheduling and Triggers The IADC has several triggering options available for both the Single queue and the Scan queue. When a conversion trigger occurs and there are no other conversions active or pending, the request is serviced immediately. If both the single and scan queues are being used in an application, it is possible to serve the conversion requests as needed, and specify their priority.
  • Page 629 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3.3.1 Conversion Triggering Examples Scheduling a Single Sample The simplest use case for the IADC is performing one conversion on-demand from the Single queue. Figure 23.5 Immediate Single Conversion on page 629 shows the configuration and timing of this use case.
  • Page 630 Reference Manual IADC - Incremental Analog to Digital Converter Periodic Scans Another common use case is to periodically trigger the IADC to perform a multi-channel scan. Figure 23.6 Periodic Scan Example on page 630 shows the timing of a periodic scan triggered by the IADC's local timer. The scanner is configured to sample four different channels;...
  • Page 631 Reference Manual IADC - Incremental Analog to Digital Converter Tailgating Examples An example using conversion tailgating is shown in Figure 23.7 Simple Conversion with Tailgating Enabled on page 631. In the ex- ample, the Scan queue is configured to trigger a two-channel conversion periodically on the IADC local timer, while the Single queue is configured to trigger on-demand from software.
  • Page 632 Reference Manual IADC - Incremental Analog to Digital Converter SINGLE and SCAN use different triggers PRS pushes out TMR timing sample TIMER PRS1 SCANQEN SINGLEQEN positive negative QUEUE mask port port Trigger Source trigger action SCAN INTERNAL TIMER once SINGLE PRSPOS once warmup, or changing between configurations...
  • Page 633: Reference Selection And Analog Gain

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.4 Reference Selection and Analog Gain The default IADC reference is to use the internal band gap circuit. The analog power supply voltage can also be used as a voltage reference. The reference voltage is selected using the REFSEL field in IADC_CFGx. Refer to Table 23.1 Mode Settings on page 633.
  • Page 634 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.5.2 Internal and Dedicated Inputs Internal signals and dedicated inputs are not routed through the shared ABUS resources. In general, these resources are selected di- rectly by the settings of PORTPOS and PORTNEG, while the PINPOS and PINNEG fields are not used. When PORTPOS is set to SUPPLY, PINPOS is used to select which of the power supplies is connected.
  • Page 635 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.5.3 Input Selection Examples When configuring to measure a single-ended signal, the positive input selection should always point to the desired input, and PORT- NEG should be programmed to GND. Correct configuration examples for single-ended conversions are shown in Figure 23.10 Single Ended Port/Pin Selection Odd Channel on page 635 Figure 23.11 Single Ended Port/Pin Selection Even Channel on page...
  • Page 636 Reference Manual IADC - Incremental Analog to Digital Converter Single Ended Polarity Error GPIOCTRL: Positive Negative CD_ODD1 to ADC port port A_EVEN0 A_EVEN1 even VINT=GND CD_ODD0 Result = CD_ODD1 POLARITYERROR Single Ended is only allowed on positive side Figure 23.12. Single Ended Port/Pin Selection Polarity Error Correct configuration examples for single-ended conversions are shown in Figure 23.13 Differential Port/Pin Selection without Swap on page 636...
  • Page 637 Reference Manual IADC - Incremental Analog to Digital Converter Differential GPIOCTRL: A_EVEN0 to ADC Positive Negative CD_ODD0 to ADC port port A0_EVEN A1_EVEN even C0_ODD C1_ODD Figure 23.14. Differential Port/Pin Selection with Swap Figure 23.15 Differential Port/Pin Selection Polarity Error on page 637 shows an example where the both the positive and the nega- tive input selections point to ODD buses.
  • Page 638: Gain And Offset Correction

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.5.4 Scan Queue The scan queue allows the IADC to automatically convert up to 16 channels in sequence without CPU intervention. Input and configura- tion selection for each channel in the scan table is specified by the IADC_SCANx register for that channel (channel 0 is configured with IADC_SCAN0, channel 1 is configured with IADC_SCAN1, and so on).
  • Page 639 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.6.1.1 Gain Correction The IADC gain error is designed to be minimal with the digital gain correction set to 1.0 (GAIN3MSB = 1 and GAIN13LSB = 0). Tighter gain error is achieved by adjusting these values in IADC_SCALEx. Using this gain correction mechanism will result in a slight increase to the DNL of the converter, which is reduced by higher OSR settings.
  • Page 640 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.6.1.2 Offset Correction Offset is impacted by the selected ANALOGGAIN and OSR settings in IADC_CFGx, the GAIN3MSB and GAIN13LSB values in IADC_SCALEx, and the voltage reference. Offset is production calibrated for any combination of possibilities, but the OFFSET register value must be calculated for the given situation before it can be effectively used.
  • Page 641 Reference Manual IADC - Incremental Analog to Digital Converter Step 4: Calculate total offset by adding the analog offset to the systematic offset. Systematic offset is a fixed number dependent on OSR, and calculated according to the following equation: off_sys = 640*(256/OSR) Total uncorrected offset (off_tot) is calculated by: off_tot = (off_ana * 4 + off_sys) Step 5: Apply gain error correction, if needed.
  • Page 642: Output Data Fifos

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.7 Output Data FIFOs The single and scan queues each have a four-word data FIFO. Conversions results are written to the output data FIFO associated with the queue. Single queue results are written to the single FIFO and scan queue results are written to the scan data FIFO. The two queues are identical in operation, but independent.
  • Page 643 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.7.1 Data Alignment and Channel ID The IADC has data alignment options and the ability to include a channel ID along with the conversion data. For the single queue, alignment and channel ID are configured in the IADC_SINGLEFIFOCFG register. For the scan queue, alignment and channel ID are configured in the IADC_SCANFIFOCFG register.
  • Page 644: Window Compare

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.8 Window Compare The IADC has a window comparison unit that can trigger interrupts conditional on the output data of the converter. The window compar- ison unit has two thresholds - greater than or equal (ADGT), and less than or equal (ADLT), which are programmable through the IADC_CMPTHR register.
  • Page 645: Interrupts

    Reference Manual IADC - Incremental Analog to Digital Converter 23.3.9 Interrupts Interrupts are enabled in the IADC_IEN register, allowing interrupts to be generated on several different IADC conditions. Each of the flags in IADC_IF has a corresponding enable bit in the IADC_IEN register. A brief overview of the available interrupt sources is shown in the list below;...
  • Page 646: Register Map

    Reference Manual IADC - Incremental Analog to Digital Converter 23.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 IADC_IPVERSION IPVERSION 0x004 IADC_EN RW ENABLE Enable 0x008 IADC_CTRL Control 0x00C IADC_CMD W SYNC Command 0x010...
  • Page 647 Reference Manual IADC - Incremental Analog to Digital Converter Offset Name Type Description 0x1028 IADC_IEN_SET Interrupt Enable 0x102C IADC_TRIGGER_SET RW CONFIG Trigger 0x1048 IADC_CFGx_SET RW CONFIG Configuration 0x1050 IADC_SCALEx_SET RW CONFIG Scaling 0x1054 IADC_SCHEDx_SET RW CONFIG Scheduling 0x1070 IADC_SINGLEFIFOCFG_SET RW CONFIG Single FIFO Configuration 0x1074 IADC_SINGLEFIFODATA_SET...
  • Page 648 Reference Manual IADC - Incremental Analog to Digital Converter Offset Name Type Description 0x208C IADC_SCANDATA_CLR RH SYNC Scan Data 0x2098 IADC_SINGLE_CLR RW SYNC Single Queue Port Selection 0x20A0 IADC_SCANx_CLR RW CONFIG SCAN Entry 0x3000 IADC_IPVERSION_TGL IPVERSION 0x3004 IADC_EN_TGL RW ENABLE Enable 0x3008 IADC_CTRL_TGL...
  • Page 649: Register Description

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5 Register Description 23.5.1 IADC_IPVERSION - IPVERSION Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
  • Page 650: Iadc_Ctrl - Control

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.3 IADC_CTRL - Control Offset Bit Position 0x008 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 30:28 HSCLKRATE...
  • Page 651 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description ADC behavior when halted by debugger. Value Mode Description NORMAL Continue operation as normal during debug mode HALT Complete the current conversion and then halt during debug mode ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1...
  • Page 652: Iadc_Cmd - Command

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.4 IADC_CMD - Command Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TIMERDIS...
  • Page 653: Iadc_Timer - Timer

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.5 IADC_TIMER - Timer Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0...
  • Page 654: Iadc_Status - Status

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.6 IADC_STATUS - Status Offset Bit Position 0x014 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions ADCWARM ADCWARM...
  • Page 655: Iadc_Maskreq - Mask Request

    Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description The ADC is warmed up and in the process of performing a conversion. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SCANQUEUEPENDING 0x0...
  • Page 656: Iadc_Stmask - Scan Table Mask

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.8 IADC_STMASK - Scan Table Mask Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0...
  • Page 657: Iadc_If - Interrupt Flags

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.10 IADC_IF - Interrupt Flags Offset Bit Position 0x024 Reset Access Name Name Reset Access Description EM23ABORTERROR EM2/3 Abort Error The system entered EM2 or EM3 during a conversion with an unsupported clock. Conversion results may be corrupted. 30:20 Reserved To ensure compatibility with future devices, always write bits to 0.
  • Page 658 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SCANCMP Scan Result Window Compare Scan digital compare window tripped. SINGLECMP Single Result Window Compare Single digital compare window tripped.
  • Page 659: Iadc_Ien - Interrupt Enable

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.11 IADC_IEN - Interrupt Enable Offset Bit Position 0x028 Reset Access Name Name Reset Access Description EM23ABORTERROR EM2/3 Abort Error Enable EM2/3 Abort Error Enable 30:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SCANFIFOUF...
  • Page 660 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SCANCMP Scan Result Window Compare Enable Scan Result Window Compare Enable SINGLECMP Single Result Window Compare Enable Single Result Window Compare Enable...
  • Page 661: Iadc_Trigger - Trigger

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.12 IADC_TRIGGER - Trigger Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SINGLETAILGATE...
  • Page 662 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. TIMER Triggers when the timer count reaches zero. PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the...
  • Page 663 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization.
  • Page 664: Iadc_Cfgx - Configuration

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.13 IADC_CFGx - Configuration Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 29:28...
  • Page 665 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description ANAGAIN2 Analog gain of 2x. ANAGAIN3 Analog gain of 3x. ANAGAIN4 Analog gain of 4x. 11:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions OSRHS...
  • Page 666: Iadc_Scalex - Scaling

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.14 IADC_SCALEx - Scaling Offset Bit Position 0x050 Reset Access Name Name Reset Access Description GAIN3MSB Gain 3 MSBs 3 MSBs of the 16-bit gain value (0=011 or 0.75; 1=1xx or 1.00). Example {GAIN3MSB, GAIN13LSB} = {100, 0_1001_0000_0000} = 1.07031x.
  • Page 667: Iadc_Singlefifocfg - Single Fifo Configuration

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.16 IADC_SINGLEFIFOCFG - Single FIFO Configuration Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DMAWUFIFOSINGLE...
  • Page 668: Iadc_Singlefifodata - Single Fifo Read Data

    Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] LEFT12 DATA[11:0], 000000000000, ID[7:0] 23.5.17 IADC_SINGLEFIFODATA - Single FIFO Read Data Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:0 DATA R(r) Data...
  • Page 669: Iadc_Singledata - Single Data

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.19 IADC_SINGLEDATA - Single Data Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:0 DATA Data Reads the most recent data word from the single FIFO, but does not pop a value. Even if the FIFO has overflowed and stopped updating, the most recent conversion will continue to overwrite SINGLEDATA.
  • Page 670: Iadc_Scanfifocfg - Scan Fifo Configuration

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.20 IADC_SCANFIFOCFG - Scan FIFO Configuration Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DMAWUFIFOSCAN...
  • Page 671: Iadc_Scanfifodata - Scan Fifo Read Data

    Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] LEFT12 DATA[11:0], 000000000000, ID[7:0] 23.5.21 IADC_SCANFIFODATA - Scan FIFO Read Data Offset Bit Position 0x084 Reset Access Name Name Reset Access Description 31:0 DATA R(r) Data...
  • Page 672: Iadc_Scandata - Scan Data

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.23 IADC_SCANDATA - Scan Data Offset Bit Position 0x08C Reset Access Name Name Reset Access Description 31:0 DATA Data Reads the most recent data word from the scan FIFO, but does not pop a value. Even if the FIFO has overflowed and stopped updating, the most recent conversion will continue to overwrite SCANDATA.
  • Page 673: Iadc_Single - Single Queue Port Selection

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.24 IADC_SINGLE - Single Queue Port Selection Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Comparison Enable...
  • Page 674 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description PORTB Port B - Select pin number using PINNEG PORTC Port C - Select pin number using PINNEG PORTD Port D - Select pin number using PINNEG PINNEG Negative Pin Select Pin number for the negative input of the ADC.
  • Page 675: Iadc_Scanx - Scan Entry

    Reference Manual IADC - Incremental Analog to Digital Converter 23.5.25 IADC_SCANx - SCAN Entry Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Comparison Enable...
  • Page 676 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description PORTB Port B - Select pin number using PINNEG PORTC Port C - Select pin number using PINNEG PORTD Port D - Select pin number using PINNEG PINNEG Negative Pin Select Pin number for the negative input of the ADC.
  • Page 677: Gpio - General Purpose Input/Output

    Reference Manual GPIO - General Purpose Input/Output 24. GPIO - General Purpose Input/Output Quick Facts What? The General Purpose Input/Output (GPIO) is used for pin configuration, direct pin manipulation, and sensing, as well as routing for peripheral pin connec- tions. Why? Easy to use and highly configurable input/output pins are important to fit many communication proto-...
  • Page 678: Features

    Reference Manual GPIO - General Purpose Input/Output 24.2 Features • Individual configuration for each pin • Tristate (reset state) • Push-pull • Open-drain • Pull-up resistor • Pull-down resistor • Programable Slewrate Control • EM4 IO pin retention • Output enable •...
  • Page 679: Functional Description

    Reference Manual GPIO - General Purpose Input/Output 24.3 Functional Description An overview of the GPIO module is shown in Figure 24.1 Pin Configuration on page 679. The GPIO pins are grouped into 16-pin ports. Each individual GPIO pin is called Pxn where x indicates the port (A, B, C ...) and n indicates the pin number (0,1,..,15). Fewer than 16 pins may be available on some ports depending on the total number of I/O pins on the package.
  • Page 680: Pin Configuration

    Reference Manual GPIO - General Purpose Input/Output 24.3.1 Pin Configuration In addition to setting the pins as either outputs or inputs, the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations. GPIO_Px_MODEL contains 8 bit fields named MODEn (n=0,1,..7) which control pins 0-7, while GPIO_Px_MODEH contains 8 bit fields named MODEn (n=8,9,..15) which control pins 8-15.
  • Page 681 Reference Manual GPIO - General Purpose Input/Output the input of a GPIO port. The pull-up, pull-down and glitch filter function can optionally be applied to the input, see Figure 24.2 Tristated Output with Optional Pull-up or Pull-down on page 681. Filter enable Optional Input enable...
  • Page 682: Alternate Port Control

    Reference Manual GPIO - General Purpose Input/Output 24.3.2 Alternate Port Control The Alternate Port Control allows for additional flexibility of port level settings. A user may setup two different port configurations (nor- mal and alternate modes) and select which is applied on a pin by pin bases. For example you may configure half of port A to use the slowest slew rate while the other half uses a faster slew rate.
  • Page 683: Em4 Wakeup

    Reference Manual GPIO - General Purpose Input/Output 24.3.8 EM4 Wakeup It is possible to trigger a wake-up from EM4 using any of the selectable EM4WU GPIO pins. The wake-up request can be triggered through the pins by enabling the corresponding bit in the GPIO_EM4WUEN register. When EM4 wake-up is enabled for the pin, the input filter is enabled during EM4.
  • Page 684: Interrupt Generation

    Reference Manual GPIO - General Purpose Input/Output 24.3.9.4 ETM Trace Connections There is a single trace pin available on the device. One trace clock which can be enabled by setting the TRACECLKPEN bit-field in GPIO_TRACEROUTEPEN. The data pin can be enabled individually by setting TRACEDATA0PEN in GPIO_TRACEROUTEPEN. The trace pins are fixed location resources connected to specific pins.
  • Page 685: Output To Prs

    Reference Manual GPIO - General Purpose Input/Output 24.3.10.2 Level Interrupt Generation GPIO can generate a level interrupt using the input of any GPIO EM4 wake-up pin on the device. The interrupts have asynchronous sense capability, enabling wake-up from energy modes as low as EM4. In order to enable the level interrupt, set the EM4WU field in the GPIO_IEN register and the EM4WUn field in the GPIO_EXTILEVEL register.
  • Page 686 Reference Manual GPIO - General Purpose Input/Output 24.3.12.1 Digital Bus (DBUS) The Digital Bus (DBUS) is an any-to-any switch matrix between peripheral resources and GPIO pins as shown in Figure 24.7 Digital Bus Interconnect on page 686. There are two DBUSes on the EFR32xG21 - one serving ports A and B and the other ports C and D. Not all peripherals have access to both DBUSes.
  • Page 687: Synchronization

    Reference Manual GPIO - General Purpose Input/Output 24.4 Synchronization To avoid metastability in synchronous logic connected to the pins, all inputs are synchronized with double flip-flops. The flip-flops for the input data run on these HFBUSCLK. Consequently, when a pin changes state, the change will propagate to GPIO_Px_DIN after two 2 HFBUSCLK cycles.
  • Page 688: Register Map

    Reference Manual GPIO - General Purpose Input/Output 24.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_PORTA_CTRL Port control 0x004 GPIO_PORTA_MODEL mode low 0x010 GPIO_PORTA_DOUT data out 0x014 GPIO_PORTA_DIN data in 0x030 GPIO_PORTB_CTRL Port control...
  • Page 689 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x460 GPIO_ACMP1_ACMPOUT- ACMPOUT port/pin select ROUTE 0x468 GPIO_CMU_ROUTEEN CMU pin enable 0x46C GPIO_CMU_CLKIN0ROUTE CLKIN0 port/pin select 0x470 GPIO_CMU_CLKOUT0ROUTE CLKOUT0 port/pin select 0x474 GPIO_CMU_CLKOUT1ROUTE CLKOUT1 port/pin select 0x478 GPIO_CMU_CLKOUT2ROUTE CLKOUT2 port/pin select 0x484 GPIO_FRC_ROUTEEN FRC pin enable...
  • Page 690 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x510 GPIO_PRS0_ASYNCH10ROUT ASYNCH10 port/pin select 0x514 GPIO_PRS0_ASYNCH11ROUT ASYNCH11 port/pin select 0x518 GPIO_PRS0_SYNCH0ROUTE SYNCH0 port/pin select 0x51C GPIO_PRS0_SYNCH1ROUTE SYNCH1 port/pin select 0x520 GPIO_PRS0_SYNCH2ROUTE SYNCH2 port/pin select 0x524 GPIO_PRS0_SYNCH3ROUTE SYNCH3 port/pin select 0x52C GPIO_TIMER0_ROUTEEN TIMER0 pin enable...
  • Page 691 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x5B4 GPIO_USART0_CTSROUTE CTS port/pin select 0x5B8 GPIO_USART0_RTSROUTE RTS port/pin select 0x5BC GPIO_USART0_RXROUTE RX port/pin select 0x5C0 GPIO_USART0_CLKROUTE CLK port/pin select 0x5C4 GPIO_USART0_TXROUTE TX port/pin select 0x5CC GPIO_USART1_ROUTEEN USART1 pin enable 0x5D0 GPIO_USART1_CSROUTE CS port/pin select...
  • Page 692 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1320 GPIO_ABUSALLOC_SET A Bus allocation 0x1324 GPIO_BBUSALLOC_SET B Bus allocation 0x1328 GPIO_CDBUSALLOC_SET CD Bus allocation 0x1400 GPIO_EXTIPSELL_SET External Interrupt Port Select Low 0x1408 GPIO_EXTIPINSELL_SET External Interrupt Pin Select Low 0x1410 GPIO_EXTIRISE_SET External Interrupt Rising Edge Trigger...
  • Page 693 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x14B8 GPIO_LETIMER0_ROU- LETIMER pin enable TEEN_SET 0x14BC GPIO_LETIM- OUT0 port/pin select ER0_OUT0ROUTE_SET 0x14C0 GPIO_LETIM- OUT1 port/pin select ER0_OUT1ROUTE_SET 0x14C8 GPIO_MODEM_ROUTEEN_SET MODEM pin enable 0x14CC GPIO_MO- ANT0 port/pin select DEM_ANT0ROUTE_SET 0x14D0 GPIO_MO- ANT1 port/pin select DEM_ANT1ROUTE_SET...
  • Page 694 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1520 GPIO_PRS0_SYNCH2ROUTE_ SYNCH2 port/pin select 0x1524 GPIO_PRS0_SYNCH3ROUTE_ SYNCH3 port/pin select 0x152C GPIO_TIMER0_ROUTEEN_SET TIMER0 pin enable 0x1530 GPIO_TIM- CC0 port/pin select ER0_CC0ROUTE_SET 0x1534 GPIO_TIM- CC1 port/pin select ER0_CC1ROUTE_SET 0x1538 GPIO_TIM- CC2 port/pin select ER0_CC2ROUTE_SET 0x153C GPIO_TIM-...
  • Page 695 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1594 GPIO_TIM- CC1 port/pin select ER3_CC1ROUTE_SET 0x1598 GPIO_TIM- CC2 port/pin select ER3_CC2ROUTE_SET 0x159C GPIO_TIM- CDTI0 port/pin select ER3_CDTI0ROUTE_SET 0x15A0 GPIO_TIM- CDTI1 port/pin select ER3_CDTI1ROUTE_SET 0x15A4 GPIO_TIM- CDTI2 port/pin select ER3_CDTI2ROUTE_SET 0x15AC GPIO_USART0_ROU- USART0 pin enable...
  • Page 696 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1600 GPIO_USART2_CLKROUTE_SE CLK port/pin select 0x1604 GPIO_USART2_TXROUTE_SET TX port/pin select 0x2000 GPIO_PORTA_CTRL_CLR Port control 0x2004 GPIO_PORTA_MODEL_CLR mode low 0x2010 GPIO_PORTA_DOUT_CLR data out 0x2014 GPIO_PORTA_DIN_CLR data in 0x2030 GPIO_PORTB_CTRL_CLR Port control 0x2034 GPIO_PORTB_MODEL_CLR mode low...
  • Page 697 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x2460 GPIO_ACMP1_ACMPOUT- ACMPOUT port/pin select ROUTE_CLR 0x2468 GPIO_CMU_ROUTEEN_CLR CMU pin enable 0x246C GPIO_CMU_CLKIN0ROUTE_CL CLKIN0 port/pin select 0x2470 GPIO_CMU_CLKOUT0ROUTE_ CLKOUT0 port/pin select 0x2474 GPIO_CMU_CLKOUT1ROUTE_ CLKOUT1 port/pin select 0x2478 GPIO_CMU_CLKOUT2ROUTE_ CLKOUT2 port/pin select 0x2484 GPIO_FRC_ROUTEEN_CLR FRC pin enable...
  • Page 698 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x24F0 GPIO_PRS0_ASYNCH2ROUTE ASYNCH2 port/pin select _CLR 0x24F4 GPIO_PRS0_ASYNCH3ROUTE ASYNCH3 port/pin select _CLR 0x24F8 GPIO_PRS0_ASYNCH4ROUTE ASYNCH4 port/pin select _CLR 0x24FC GPIO_PRS0_ASYNCH5ROUTE ASYNCH5 port/pin select _CLR 0x2500 GPIO_PRS0_ASYNCH6ROUTE ASYNCH6 port/pin select _CLR 0x2504 GPIO_PRS0_ASYNCH7ROUTE...
  • Page 699 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x2558 GPIO_TIM- CC2 port/pin select ER1_CC2ROUTE_CLR 0x255C GPIO_TIM- CDTI0 port/pin select ER1_CDTI0ROUTE_CLR 0x2560 GPIO_TIM- CDTI1 port/pin select ER1_CDTI1ROUTE_CLR 0x2564 GPIO_TIM- CDTI2 port/pin select ER1_CDTI2ROUTE_CLR 0x256C GPIO_TIMER2_ROUTEEN_CLR TIMER2 pin enable 0x2570 GPIO_TIM- CC0 port/pin select...
  • Page 700 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x25C4 GPIO_USART0_TXROUTE_CLR TX port/pin select 0x25CC GPIO_USART1_ROU- USART1 pin enable TEEN_CLR 0x25D0 GPIO_USART1_CSROUTE_CL CS port/pin select 0x25D4 GPIO_USART1_CTSROUTE_CL CTS port/pin select 0x25D8 GPIO_USART1_RTSROUTE_CL RTS port/pin select 0x25DC GPIO_USART1_RXROUTE_CL RX port/pin select 0x25E0 GPIO_USART1_CLKROUTE_CL CLK port/pin select...
  • Page 701 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x30A4 GPIO_PORTD_DIN_TGL data in 0x3300 GPIO_LOCK_TGL main 0x3310 GPIO_GPIOLOCKSTATUS_TGL Lock Status 0x3320 GPIO_ABUSALLOC_TGL A Bus allocation 0x3324 GPIO_BBUSALLOC_TGL B Bus allocation 0x3328 GPIO_CDBUSALLOC_TGL CD Bus allocation 0x3400 GPIO_EXTIPSELL_TGL External Interrupt Port Select Low 0x3408 GPIO_EXTIPINSELL_TGL External Interrupt Pin Select Low...
  • Page 702 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x34AC GPIO_I2C1_SCLROUTE_TGL SCL port/pin select 0x34B0 GPIO_I2C1_SDAROUTE_TGL SDA port/pin select 0x34B8 GPIO_LETIMER0_ROU- LETIMER pin enable TEEN_TGL 0x34BC GPIO_LETIM- OUT0 port/pin select ER0_OUT0ROUTE_TGL 0x34C0 GPIO_LETIM- OUT1 port/pin select ER0_OUT1ROUTE_TGL 0x34C8 GPIO_MODEM_ROUTEEN_TGL MODEM pin enable 0x34CC GPIO_MO- ANT0 port/pin select...
  • Page 703 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x351C GPIO_PRS0_SYNCH1ROUTE_ SYNCH1 port/pin select 0x3520 GPIO_PRS0_SYNCH2ROUTE_ SYNCH2 port/pin select 0x3524 GPIO_PRS0_SYNCH3ROUTE_ SYNCH3 port/pin select 0x352C GPIO_TIMER0_ROUTEEN_TGL TIMER0 pin enable 0x3530 GPIO_TIM- CC0 port/pin select ER0_CC0ROUTE_TGL 0x3534 GPIO_TIM- CC1 port/pin select ER0_CC1ROUTE_TGL 0x3538 GPIO_TIM-...
  • Page 704 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x3590 GPIO_TIM- CC0 port/pin select ER3_CC0ROUTE_TGL 0x3594 GPIO_TIM- CC1 port/pin select ER3_CC1ROUTE_TGL 0x3598 GPIO_TIM- CC2 port/pin select ER3_CC2ROUTE_TGL 0x359C GPIO_TIM- CDTI0 port/pin select ER3_CDTI0ROUTE_TGL 0x35A0 GPIO_TIM- CDTI1 port/pin select ER3_CDTI1ROUTE_TGL 0x35A4 GPIO_TIM-...
  • Page 705: Register Description

    Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x35FC GPIO_USART2_RXROUTE_TG RX port/pin select 0x3600 GPIO_USART2_CLKROUTE_T CLK port/pin select 0x3604 GPIO_USART2_TXROUTE_TGL TX port/pin select 24.6 Register Description 24.6.1 GPIO_PORTA_CTRL - Port control Offset Bit Position 0x000 Reset Access Name Name Reset...
  • Page 706: Gpio_Porta_Model - Mode Low

    Reference Manual GPIO - General Purpose Input/Output 24.6.2 GPIO_PORTA_MODEL - mode low Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:24 MODE6...
  • Page 707 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
  • Page 708 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set. INPUTPULL Input enabled. DOUT determines pull direction. INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output.
  • Page 709 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup. FILTER MODE1 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
  • Page 710: Gpio_Porta_Dout - Data Out

    Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDPULLUP Open-drain output with pullup. WIREDANDPULLUPFIL- Open-drain output with filter and pullup. WIREDANDALT Open-drain output using alternate control. WIREDANDALTFILTER Open-drain output using alternate control with filter. WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup.
  • Page 711: Gpio_Portb_Ctrl - Port Control

    Reference Manual GPIO - General Purpose Input/Output 24.6.5 GPIO_PORTB_CTRL - Port control Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DINDISALT Data In Disable Alt...
  • Page 712: Gpio_Portb_Model - Mode Low

    Reference Manual GPIO - General Purpose Input/Output 24.6.6 GPIO_PORTB_MODEL - mode low Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions MODE1 MODE n...
  • Page 713: Gpio_Portb_Dout - Data Out

    Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
  • Page 714: Gpio_Portb_Din - Data

    Reference Manual GPIO - General Purpose Input/Output 24.6.8 GPIO_PORTB_DIN - data in Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Data input Data input...
  • Page 715: Gpio_Portc_Ctrl - Port Control

    Reference Manual GPIO - General Purpose Input/Output 24.6.9 GPIO_PORTC_CTRL - Port control Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DINDISALT Data In Disable Alt...
  • Page 716: Gpio_Portc_Model - Mode Low

    Reference Manual GPIO - General Purpose Input/Output 24.6.10 GPIO_PORTC_MODEL - mode low Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:20 MODE5...
  • Page 717 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
  • Page 718 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set. INPUTPULL Input enabled. DOUT determines pull direction. INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output.
  • Page 719: Gpio_Portc_Dout - Data Out

    Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup. FILTER MODE0 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
  • Page 720: Gpio_Portc_Din - Data In

    Reference Manual GPIO - General Purpose Input/Output 24.6.12 GPIO_PORTC_DIN - data in Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions Data input Data input...
  • Page 721: Gpio_Portd_Ctrl - Port Control

    Reference Manual GPIO - General Purpose Input/Output 24.6.13 GPIO_PORTD_CTRL - Port control Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DINDISALT Data In Disable Alt...
  • Page 722: Gpio_Portd_Model - Mode Low

    Reference Manual GPIO - General Purpose Input/Output 24.6.14 GPIO_PORTD_MODEL - mode low Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16 MODE4...
  • Page 723 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
  • Page 724 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set. INPUTPULL Input enabled. DOUT determines pull direction. INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output.
  • Page 725: Gpio_Portd_Dout - Data Out

    Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup. FILTER 24.6.15 GPIO_PORTD_DOUT - data out Offset Bit Position 0x0A0 Reset Access Name Name...
  • Page 726: Gpio_Lock - Main

    Reference Manual GPIO - General Purpose Input/Output 24.6.17 GPIO_LOCK - main Offset Bit Position 0x300 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0 LOCKKEY...
  • Page 727: Gpio_Abusalloc - A Bus Allocation

    Reference Manual GPIO - General Purpose Input/Output 24.6.19 GPIO_ABUSALLOC - A Bus allocation Offset Bit Position 0x320 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:24...
  • Page 728 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ACMP0 The bus is allocated to ACMP0 ACMP1 The bus is allocated to ACMP1 DEBUG DEBUG mode, bus allocated to all clients Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions AEVEN0...
  • Page 729: Gpio_Bbusalloc - B Bus Allocation

    Reference Manual GPIO - General Purpose Input/Output 24.6.20 GPIO_BBUSALLOC - B Bus allocation Offset Bit Position 0x324 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:24...
  • Page 730 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ACMP1 The bus is allocated to ACMP1 DEBUG DEBUG mode, bus allocated to all clients Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions BEVEN0...
  • Page 731: Gpio_Cdbusalloc - Cd Bus Allocation

    Reference Manual GPIO - General Purpose Input/Output 24.6.21 GPIO_CDBUSALLOC - CD Bus allocation Offset Bit Position 0x328 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:24...
  • Page 732 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ACMP0 The bus is allocated to ACMP0 ACMP1 The bus is allocated to ACMP1 DEBUG DEBUG mode, bus allocated to all clients Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CDEVEN0...
  • Page 733: Gpio_Extipsell - External Interrupt Port Select Low

    Reference Manual GPIO - General Purpose Input/Output 24.6.22 GPIO_EXTIPSELL - External Interrupt Port Select Low Offset Bit Position 0x400 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 29:28...
  • Page 734 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 17:16 EXTIPSEL4 External Interrupt Port Select Port select for external interrupt 4 (EXTI4). Value Mode Description...
  • Page 735 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions EXTIPSEL0 External Interrupt Port Select Port select for external interrupt 0 (EXTI0). Value Mode Description...
  • Page 736: Gpio_Extipinsell - External Interrupt Pin Select Low

    Reference Manual GPIO - General Purpose Input/Output 24.6.23 GPIO_EXTIPINSELL - External Interrupt Pin Select Low Offset Bit Position 0x408 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 29:28...
  • Page 737 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 17:16 EXTIPINSEL4 External Interrupt Pin select OFFSET select for External Interrupt 4 (EXTI4). (See text for additional information.) Value Mode Description...
  • Page 738: Gpio_Extirise - External Interrupt Rising Edge Trigger

    Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions EXTIPINSEL0 External Interrupt Pin select OFFSET select for External Interrupt 0 (EXTI0). (See text for additional information.) Value Mode Description...
  • Page 739: Gpio_Extifall - External Interrupt Falling Edge Trigger

    Reference Manual GPIO - General Purpose Input/Output 24.6.25 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Offset Bit Position 0x414 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions EXTIFALL...
  • Page 740: Gpio_Ien - Interrupt Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.27 GPIO_IEN - Interrupt Enable Offset Bit Position 0x424 Reset Access Name Name Reset Access Description 31:16 EM4WUIEN EM4 Wake Up Interrupt En 15:0 EXTIEN External Pin Enable External Pin interrupt enable 24.6.28 GPIO_EM4WUEN - main Offset Bit Position 0x42C...
  • Page 741: Gpio_Em4Wupol - New Register

    Reference Manual GPIO - General Purpose Input/Output 24.6.29 GPIO_EM4WUPOL - New Register Offset Bit Position 0x430 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 27:16 EM4WUPOL...
  • Page 742: Gpio_Dbgroutepen - Debugger Route Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.30 GPIO_DBGROUTEPEN - Debugger Route Pin enable Offset Bit Position 0x440 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TDIPEN...
  • Page 743: Gpio_Traceroutepen - Trace Route Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.31 GPIO_TRACEROUTEPEN - Trace Route Pin Enable Offset Bit Position 0x444 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TRACEDATA0PEN...
  • Page 744: Gpio_Acmp0_Acmpoutroute - Acmpout Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.33 GPIO_ACMP0_ACMPOUTROUTE - ACMPOUT port/pin select Offset Bit Position 0x454 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 745: Gpio_Acmp1_Acmpoutroute - Acmpout Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.35 GPIO_ACMP1_ACMPOUTROUTE - ACMPOUT port/pin select Offset Bit Position 0x460 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 746: Gpio_Cmu_Clkin0Route - Clkin0 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.37 GPIO_CMU_CLKIN0ROUTE - CLKIN0 port/pin select Offset Bit Position 0x46C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 747: Gpio_Cmu_Clkout1Route - Clkout1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.39 GPIO_CMU_CLKOUT1ROUTE - CLKOUT1 port/pin select Offset Bit Position 0x474 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 748: Gpio_Frc_Routeen - Frc Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.41 GPIO_FRC_ROUTEEN - FRC pin enable Offset Bit Position 0x484 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DOUTPEN...
  • Page 749: Gpio_Frc_Dframeroute - Dframe Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.43 GPIO_FRC_DFRAMEROUTE - DFRAME port/pin select Offset Bit Position 0x48C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 750: Gpio_I2C0_Routeen - I2C0 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.45 GPIO_I2C0_ROUTEEN - I2C0 pin enable Offset Bit Position 0x498 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SDAPEN...
  • Page 751: Gpio_I2C0_Sdaroute - Sda Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.47 GPIO_I2C0_SDAROUTE - SDA port/pin select Offset Bit Position 0x4A0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 752: Gpio_I2C1_Sclroute - Scl Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.49 GPIO_I2C1_SCLROUTE - SCL port/pin select Offset Bit Position 0x4AC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 753: Gpio_Letimer0_Routeen - Letimer Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.51 GPIO_LETIMER0_ROUTEEN - LETIMER pin enable Offset Bit Position 0x4B8 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions OUT1PEN...
  • Page 754: Gpio_Letimer0_Out1Route - Out1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.53 GPIO_LETIMER0_OUT1ROUTE - OUT1 port/pin select Offset Bit Position 0x4C0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 755: Gpio_Modem_Ant0Route - Ant0 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.55 GPIO_MODEM_ANT0ROUTE - ANT0 port/pin select Offset Bit Position 0x4CC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 756: Gpio_Modem_Dclkroute - Dclk Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.57 GPIO_MODEM_DCLKROUTE - DCLK port/pin select Offset Bit Position 0x4D4 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 757: Gpio_Modem_Doutroute - Dout Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.59 GPIO_MODEM_DOUTROUTE - DOUT port/pin select Offset Bit Position 0x4DC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 758: Gpio_Prs0_Routeen - Prs0 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.60 GPIO_PRS0_ROUTEEN - PRS0 pin enable Offset Bit Position 0x4E4 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SYNCH3PEN...
  • Page 759: Gpio_Prs0_Asynch0Route - Asynch0 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ASYNCH2PEN ASYNCH2 pin enable control bit ASYNCH1PEN ASYNCH1 pin enable control bit ASYNCH0PEN ASYNCH0 pin enable control bit 24.6.61 GPIO_PRS0_ASYNCH0ROUTE - ASYNCH0 port/pin select Offset Bit Position 0x4E8 Reset Access Name Name...
  • Page 760: Gpio_Prs0_Asynch1Route - Asynch1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.62 GPIO_PRS0_ASYNCH1ROUTE - ASYNCH1 port/pin select Offset Bit Position 0x4EC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 761: Gpio_Prs0_Asynch3Route - Asynch3 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.64 GPIO_PRS0_ASYNCH3ROUTE - ASYNCH3 port/pin select Offset Bit Position 0x4F4 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 762: Gpio_Prs0_Asynch5Route - Asynch5 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.66 GPIO_PRS0_ASYNCH5ROUTE - ASYNCH5 port/pin select Offset Bit Position 0x4FC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 763: Gpio_Prs0_Asynch7Route - Asynch7 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.68 GPIO_PRS0_ASYNCH7ROUTE - ASYNCH7 port/pin select Offset Bit Position 0x504 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 764: Gpio_Prs0_Asynch9Route - Asynch9 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.70 GPIO_PRS0_ASYNCH9ROUTE - ASYNCH9 port/pin select Offset Bit Position 0x50C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 765: Gpio_Prs0_Asynch11Route - Asynch11 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.72 GPIO_PRS0_ASYNCH11ROUTE - ASYNCH11 port/pin select Offset Bit Position 0x514 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 766: Gpio_Prs0_Synch1Route - Synch1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.74 GPIO_PRS0_SYNCH1ROUTE - SYNCH1 port/pin select Offset Bit Position 0x51C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 767: Gpio_Prs0_Synch3Route - Synch3 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.76 GPIO_PRS0_SYNCH3ROUTE - SYNCH3 port/pin select Offset Bit Position 0x524 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 768: Gpio_Timer0_Routeen - Timer0 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.77 GPIO_TIMER0_ROUTEEN - TIMER0 pin enable Offset Bit Position 0x52C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CDTI2PEN...
  • Page 769: Gpio_Timer0_Cc0Route - Cc0 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.78 GPIO_TIMER0_CC0ROUTE - CC0 port/pin select Offset Bit Position 0x530 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 770: Gpio_Timer0_Cc2Route - Cc2 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.80 GPIO_TIMER0_CC2ROUTE - CC2 port/pin select Offset Bit Position 0x538 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 771: Gpio_Timer0_Cdti1Route - Cdti1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.82 GPIO_TIMER0_CDTI1ROUTE - CDTI1 port/pin select Offset Bit Position 0x540 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 772: Gpio_Timer1_Routeen - Timer1 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.84 GPIO_TIMER1_ROUTEEN - TIMER1 pin enable Offset Bit Position 0x54C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CDTI2PEN...
  • Page 773: Gpio_Timer1_Cc0Route - Cc0 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.85 GPIO_TIMER1_CC0ROUTE - CC0 port/pin select Offset Bit Position 0x550 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 774: Gpio_Timer1_Cc2Route - Cc2 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.87 GPIO_TIMER1_CC2ROUTE - CC2 port/pin select Offset Bit Position 0x558 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 775: Gpio_Timer1_Cdti1Route - Cdti1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.89 GPIO_TIMER1_CDTI1ROUTE - CDTI1 port/pin select Offset Bit Position 0x560 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 776: Gpio_Timer2_Routeen - Timer2 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.91 GPIO_TIMER2_ROUTEEN - TIMER2 pin enable Offset Bit Position 0x56C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CDTI2PEN...
  • Page 777: Gpio_Timer2_Cc0Route - Cc0 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.92 GPIO_TIMER2_CC0ROUTE - CC0 port/pin select Offset Bit Position 0x570 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 778: Gpio_Timer2_Cc2Route - Cc2 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.94 GPIO_TIMER2_CC2ROUTE - CC2 port/pin select Offset Bit Position 0x578 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 779: Gpio_Timer2_Cdti1Route - Cdti1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.96 GPIO_TIMER2_CDTI1ROUTE - CDTI1 port/pin select Offset Bit Position 0x580 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 780: Gpio_Timer3_Routeen - Timer3 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.98 GPIO_TIMER3_ROUTEEN - TIMER3 pin enable Offset Bit Position 0x58C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CDTI2PEN...
  • Page 781: Gpio_Timer3_Cc0Route - Cc0 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.99 GPIO_TIMER3_CC0ROUTE - CC0 port/pin select Offset Bit Position 0x590 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 782: Gpio_Timer3_Cc2Route - Cc2 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.101 GPIO_TIMER3_CC2ROUTE - CC2 port/pin select Offset Bit Position 0x598 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 783: Gpio_Timer3_Cdti1Route - Cdti1 Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.103 GPIO_TIMER3_CDTI1ROUTE - CDTI1 port/pin select Offset Bit Position 0x5A0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 784: Gpio_Usart0_Routeen - Usart0 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.105 GPIO_USART0_ROUTEEN - USART0 pin enable Offset Bit Position 0x5AC Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TXPEN...
  • Page 785: Gpio_Usart0_Ctsroute - Cts Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.107 GPIO_USART0_CTSROUTE - CTS port/pin select Offset Bit Position 0x5B4 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 786: Gpio_Usart0_Rxroute - Rx Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.109 GPIO_USART0_RXROUTE - RX port/pin select Offset Bit Position 0x5BC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 787: Gpio_Usart0_Txroute - Tx Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.111 GPIO_USART0_TXROUTE - TX port/pin select Offset Bit Position 0x5C4 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 788: Gpio_Usart1_Csroute - Cs Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.113 GPIO_USART1_CSROUTE - CS port/pin select Offset Bit Position 0x5D0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 789: Gpio_Usart1_Rtsroute - Rts Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.115 GPIO_USART1_RTSROUTE - RTS port/pin select Offset Bit Position 0x5D8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 790: Gpio_Usart1_Clkroute - Clk Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.117 GPIO_USART1_CLKROUTE - CLK port/pin select Offset Bit Position 0x5E0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 791: Gpio_Usart2_Routeen - Usart2 Pin Enable

    Reference Manual GPIO - General Purpose Input/Output 24.6.119 GPIO_USART2_ROUTEEN - USART2 pin enable Offset Bit Position 0x5EC Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions TXPEN...
  • Page 792: Gpio_Usart2_Ctsroute - Cts Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.121 GPIO_USART2_CTSROUTE - CTS port/pin select Offset Bit Position 0x5F4 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 793: Gpio_Usart2_Rxroute - Rx Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.123 GPIO_USART2_RXROUTE - RX port/pin select Offset Bit Position 0x5FC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 794: Gpio_Usart2_Txroute - Tx Port/Pin Select

    Reference Manual GPIO - General Purpose Input/Output 24.6.125 GPIO_USART2_TXROUTE - TX port/pin select Offset Bit Position 0x604 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 19:16...
  • Page 795: Ldma - Linked Dma

    Reference Manual LDMA - Linked DMA 25. LDMA - Linked DMA Quick Facts What? The LDMA controller can move data without CPU in- tervention, effectively reducing the energy consump- tion for a data transfer. Why? The LDMA can perform data transfers more energy efficiently than the CPU and allows autonomous op- Flash eration in low energy modes.
  • Page 796: Features

    Reference Manual LDMA - Linked DMA 25.1.1 Features • Flexible Source and Destination transfers • Memory-to-memory • Memory-to-peripheral • Peripheral-to-memory • Peripheral-to-peripheral • DMA transfers triggered by peripherals, software, or linked list • Single or multiple data transfers for each peripheral or software request •...
  • Page 797: Block Diagram

    Reference Manual LDMA - Linked DMA 25.2 Block Diagram An overview of the LDMA and the modules it interacts with is shown in Figure 25.1 LDMA Block Diagram on page 797. Cortex Interrupts LDMA Core Error Channel done Channel 0 Peripheral Channel 1 Peripheral...
  • Page 798: Functional Description

    Reference Manual LDMA - Linked DMA 25.3 Functional Description The Linked DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data.
  • Page 799 Reference Manual LDMA - Linked DMA 25.3.1.3 Block Size The block size defines the amount of data transferred in one arbitration. It consists of one or more DMA transfers. See 25.3.6.1 Arbitra- tion Priority for more details. 25.3.1.4 Transfer Count The descriptor transfer count defines how many DMA transfers to perform.
  • Page 800 Reference Manual LDMA - Linked DMA 25.3.1.8 Byte Swap Enabling byte swap reverses the endianness of the incoming source data read into the LDMA’s FIFO. Byte swap is only valid for trans- fer sizes of word and half-word. Note that linked structure reads are not byte swapped. B3b7 B3b0 B2b7...
  • Page 801 Reference Manual LDMA - Linked DMA 25.3.1.9 DMA Size and Source/Destination Increment Programming The DMA channels’ SIZE, SRCINC, and DSTINC bit-fields are programmed to best utilize memory resources. They provide a means for memory packing and unpacking, as well as for matching the size of data being transmitted to or received from an IO peripheral. The following figure shows how 32-bit words of data are read from a memory source into the DMA’s internal transfer FIFO, and then written out to the memory destination.
  • Page 802 Reference Manual LDMA - Linked DMA Memory Memory source source 0x200 0x200 First read transmit data= First read transmit data= DMA Controller FIFO DMA Controller FIFO destination destination 0x400 0x400 First write transmit data= First write transmit data= size[1:0] = HALF size[1:0] = HALF src_inc[1:0] = WORD src_inc[1:0] = HALF...
  • Page 803: Channel Configuration

    Reference Manual LDMA - Linked DMA 25.3.2 Channel Configuration Each DMA channel has associated configuration and loop counter registers for controlling direction of address increment , arbitration slots, and descriptor looping. 25.3.2.1 Address Increment/Decrement Normally DMA transfers increment the source and destination addresses after each DMA transfer. Each channel is also capable of dec- rementing the source and/or destination addresses after each DMA transfer.
  • Page 804: Managing Transfer Errors

    Reference Manual LDMA - Linked DMA 25.3.4.1 Peripheral Transfer Requests By default peripherals issue a Single Request (SREQ) when any data is present. For peripherals with a data buffer or FIFO this occurs any time the FIFO is not empty. Upon receiving an SREQ the LDMA will perform one DMA transfer and stop till another request is made.
  • Page 805 Reference Manual LDMA - Linked DMA Table 25.1. Arbitration Slot Order Arbslot order Arbslot1 Arbslot2 Arbslot4 Arbslot8 The top row shows the order at which the arbitration slots are executed. The remaining part of the table shows a more visual interpreta- tion of the arbitration order.
  • Page 806: Channel Descriptor Data Structure

    Reference Manual LDMA - Linked DMA 25.3.6.2 DMA Transfer Arbitration In addition to the inter channel arbitration, software can configure when the controller arbitrates during a DMA transfer. This provides reduced latency to higher priority channels when configuring low priority transfers with more arbitration cycles. The LDMA provides four bits that configure how many DMA transfers occur before it re-arbitrates.
  • Page 807 Reference Manual LDMA - Linked DMA 25.3.7.1 XFER descriptor structure This descriptor defines a typical data transfer which may be a Normal, Link, or Loop transfer. Only this structure type can be written directly into LDMA's registers by the CPU. All descriptors may be linked to. Please refer to the register descriptions for additional information.
  • Page 808 Reference Manual LDMA - Linked DMA 25.3.7.2 SYNC descriptor structure This descriptor defines an intra-channel synchronizing structure. It allows the channel to wait for some external stimulus before continu- ing on to the next descriptor. This structure is also used to provide stimulus to another channel to indicate that it may continue. For example channel 1 may be configured to transfer a header into a buffer while channel 2 is simultaneously transferring data into the same structure.
  • Page 809: Interaction With The Emu

    Reference Manual LDMA - Linked DMA Name Description This bit-field serves as the SYNCTRIG match value. A sync match triggers the load of the next linked DMA structure as specified by link_mode, when: (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN). 25.3.7.3 WRI descriptor structure This descriptor defines a write-immediate structure.
  • Page 810: Interrupts

    Reference Manual LDMA - Linked DMA 25.3.9 Interrupts The LDMA_IF Interrupt flag register contains one DONE bit for each channel and one combined ERROR bit. When enabled, these in- terrupts are available as interrupts to the M33 core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the DMA is enabled in the ARM M33 core, an interrupt will be made if one or more of the interrupt flags in LDMA_IF and their corresponding bits in LDMA_IEN are set.
  • Page 811: Descriptor Linked List

    Reference Manual LDMA - Linked DMA 25.4.2 Descriptor Linked List This example shows how to use a Linked List of descriptors. Each descriptor has a link address which points to the next descriptor in the list. A descriptor may be removed from the Linked list by altering the Link address of the one before it to point to the one after it. Descriptor Linked lists are useful when handling an array of buffers for communication data.
  • Page 812 Reference Manual LDMA - Linked DMA To start execution of the linked list of descriptors: • Write the absolute address of the first descriptor to the LINKADR field of the LDMA_CH0_LINK register • Set the LINK bit of LDMA_CH0_LINK register. •...
  • Page 813: Single Descriptor Looped Transfer 8

    Reference Manual LDMA - Linked DMA 25.4.3 Single Descriptor Looped Transfer This example demonstrates how to use looping using a single descriptor. This method allows a single DMA transfer to be repeated a specified number of times. The looping descriptor is stored in memory and reloaded by hardware. After a specified number of iterations, the transfer stops.
  • Page 814: Descriptor List With Looping

    Reference Manual LDMA - Linked DMA 25.4.4 Descriptor List with Looping This example uses a descriptor list in memory with looping over multiple descriptors. This example also uses the looping feature and continues on with the next sequential descriptor after looping completes. The descriptor list in memory is shown in figure Figure 25.7 Descriptor List with Looping on page 814.
  • Page 815: Simple Inter-Channel Synchronization

    Reference Manual LDMA - Linked DMA 25.4.5 Simple Inter-Channel Synchronization The LDMA controller features synchronization structures which allow differing channels and/or hardware events to pause a DMA se- quence, and wait for a synchronizing event to restart it. In this example DMA channel 0 and 1 are tasked with the transfer of different sets of data. Channel 0 has two transfer structures, and channel 1 just one, but channel 0 must wait until channel 1 has completed its transfer before it starts its second transfer structure.
  • Page 816 Reference Manual LDMA - Linked DMA SYNC[7] STRUCTTYPE=-SYNC STRUCTTYPE=XFER wait SYNCTRIG[7]=1 STRUCTTYPE=XFER C not fetched until sync_trig[7] is set STRUCTTYPE=SYNC STRUCTTYPE=XFER set SYNC[7] Time Figure 25.8. Simple Intra-channel Synchronization Example Both A and Y effectively start at the same time. A finishes earlier, then it links to B, which waits for the SYNCTRIG[7] bit to be set before loading C.
  • Page 817: Copy

    Reference Manual LDMA - Linked DMA 25.4.6 2D Copy The LDMA can easily perform a 2D copy using a descriptor list with looping. This set up is visualized in Figure 25.9 2D copy on page 817. For an application working with graphics, this would mean the ability to copy a rectangle of a given width and height from one picture to another.
  • Page 818 Reference Manual LDMA - Linked DMA Because the first descriptor already transferred one row, the number of looping repeats should be the desired height minus two. There- fore, LOOPCNT should be set to HEIGHT minus two before initiating the transfer. This same method is easily extended to copy multiple rectangles by linking descriptors together.
  • Page 819: Ping-Pong

    Reference Manual LDMA - Linked DMA 25.4.7 Ping-Pong Communication peripherals often use ping-pong buffers. Ping-pong buffers allow the CPU to process data in one buffer while a periph- eral transmits or receives data in the other buffer. Both transmit and receive ping-pong buffers are easily implemented using the LDMA. In either case, this requires two descriptors as shown in Figure 25.10 Infinite Ping-Pong Example on page 819.
  • Page 820: Scatter-Gather

    Reference Manual LDMA - Linked DMA continue to the second buffer. The LINK bit should be cleared to zero. Once software has loaded the first buffer, it will use the LINK- LOAD bit to load the first descriptor and transmit the data. The DONIFS need not be set in each descriptor. The DMA will stop and then generate an interrupt at the completion of each descriptor.
  • Page 821 Reference Manual LDMA - Linked DMA 25.5.1 LDMA Source Selection Details Table 25.3. LDMA Source Selection Details SOURCESEL Source Name SIGSEL Request Signal Name LDMAXBAR LDMAXBAR_DMA_PRSREQ0 LDMAXBAR_DMA_PRSREQ1 TIMER0 TIMER0_DMA_CC0 TIMER0_DMA_CC1 TIMER0_DMA_CC2 TIMER0_DMA_UFOF TIMER1 TIMER1_DMA_CC0 TIMER1_DMA_CC1 TIMER1_DMA_CC2 TIMER1_DMA_UFOF USART0 USART0_DMA_RXDATAV USART0_DMA_RXDATAVRIGHT USART0_DMA_TXBL USART0_DMA_TXBLRIGHT USART0_DMA_TXEMPTY...
  • Page 822 Reference Manual LDMA - Linked DMA SOURCESEL Source Name SIGSEL Request Signal Name TIMER2 TIMER2_DMA_CC0 TIMER2_DMA_CC1 TIMER2_DMA_CC2 TIMER2_DMA_UFOF TIMER3 TIMER3_DMA_CC0 TIMER3_DMA_CC1 TIMER3_DMA_CC2 TIMER3_DMA_UFOF silabs.com | Building a more connected world. Rev. 0.4 | 822...
  • Page 823: Register Map

    Reference Manual LDMA - Linked DMA 25.6 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LDMA_IPVERSION DMA Channel Request Clear Register 0x004 LDMA_EN DMA module enable disable Register 0x008 LDMA_CTRL DMA Control Register 0x00C LDMA_STATUS...
  • Page 824 Reference Manual LDMA - Linked DMA Offset Name Type Description 0x101C LDMA_SYNCHWSEL_SET DMA Sync HW trigger selection register 0x1020 LDMA_SYNCSTATUS_SET DMA Sync Trigger Status Register 0x1024 LDMA_CHEN_SET DMA Channel Enable Register 0x1028 LDMA_CHDIS_SET DMA Channel Disable Register 0x102C LDMA_CHSTATUS_SET DMA Channel Status Register 0x1030 LDMA_CHBUSY_SET DMA Channel Busy Register...
  • Page 825 Reference Manual LDMA - Linked DMA Offset Name Type Description 0x2040 LDMA_REQDIS_CLR DMA Channel Request Disable Register 0x2044 LDMA_REQPEND_CLR DMA Channel Requests Pending Register 0x2048 LDMA_LINKLOAD_CLR DMA Channel Link Load Register 0x204C LDMA_REQCLEAR_CLR DMA Channel Request Clear Register 0x2050 LDMA_IF_CLR RWH INTFLAG Interrupt Flag Register 0x2054...
  • Page 826: Register Description

    Reference Manual LDMA - Linked DMA Offset Name Type Description 0x3068 LDMA_CHx_SRC_TGL Channel Descriptor Source Data Addres... 0x306C LDMA_CHx_DST_TGL Channel Descriptor Destination Data A... 0x3070 LDMA_CHx_LINK_TGL Channel Descriptor Link Structure Add... 25.7 Register Description 25.7.1 LDMA_IPVERSION - DMA Channel Request Clear Register Offset Bit Position 0x000...
  • Page 827: Ldma_Ctrl - Dma Control Register

    Reference Manual LDMA - Linked DMA 25.7.3 LDMA_CTRL - DMA Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description CORERST Reset DMA controller Trigger a reset of the LDMA controller core without losing register configuration 30:29 Reserved To ensure compatibility with future devices, always write bits to 0.
  • Page 828: Ldma_Status - Dma Status Register

    Reference Manual LDMA - Linked DMA 25.7.4 LDMA_STATUS - DMA Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 28:24 CHNUM...
  • Page 829: Ldma_Syncswset - Dma Sync Trig Sw Set Register

    Reference Manual LDMA - Linked DMA 25.7.5 LDMA_SYNCSWSET - DMA Sync Trig Sw Set Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SYNCSWSET...
  • Page 830: Ldma_Synchwen - Dma Sync Hw Trigger Enable Register

    Reference Manual LDMA - Linked DMA 25.7.7 LDMA_SYNCHWEN - DMA Sync HW trigger enable register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:16...
  • Page 831: Ldma_Synchwsel - Dma Sync Hw Trigger Selection Register

    Reference Manual LDMA - Linked DMA 25.7.8 LDMA_SYNCHWSEL - DMA Sync HW trigger selection register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 23:16...
  • Page 832: Ldma_Syncstatus - Dma Sync Trigger Status Register

    Reference Manual LDMA - Linked DMA 25.7.9 LDMA_SYNCSTATUS - DMA Sync Trigger Status Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions SYNCTRIG...
  • Page 833: Ldma_Chdis - Dma Channel Disable Register

    Reference Manual LDMA - Linked DMA 25.7.11 LDMA_CHDIS - DMA Channel Disable Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CHDIS...
  • Page 834: Ldma_Chbusy - Dma Channel Busy Register

    Reference Manual LDMA - Linked DMA 25.7.13 LDMA_CHBUSY - DMA Channel Busy Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions BUSY...
  • Page 835: Ldma_Chdone - Dma Channel Linking Done Register

    Reference Manual LDMA - Linked DMA 25.7.14 LDMA_CHDONE - DMA Channel Linking Done Register (Si... Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CHDONE7...
  • Page 836: Ldma_Dbghalt - Dma Channel Debug Halt Register

    Reference Manual LDMA - Linked DMA 25.7.15 LDMA_DBGHALT - DMA Channel Debug Halt Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DBGHALT...
  • Page 837: Ldma_Reqdis - Dma Channel Request Disable Register

    Reference Manual LDMA - Linked DMA 25.7.17 LDMA_REQDIS - DMA Channel Request Disable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions REQDIS...
  • Page 838: Ldma_Linkload - Dma Channel Link Load Register

    Reference Manual LDMA - Linked DMA 25.7.19 LDMA_LINKLOAD - DMA Channel Link Load Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions LINKLOAD...
  • Page 839: Ldma_If - Interrupt Flag Register

    Reference Manual LDMA - Linked DMA 25.7.21 LDMA_IF - Interrupt Flag Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description ERROR Error Flag Set to 1 on an Error 30:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DONE7...
  • Page 840: Ldma_Ien - Interrupt Enable Register

    Reference Manual LDMA - Linked DMA 25.7.22 LDMA_IEN - Interrupt Enable Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description ERROR Enable or disable the error interrupt This is the bitfield to enable the link done interrupt 30:8 Reserved To ensure compatibility with future devices, always write bits to 0.
  • Page 841: Ldma_Chx_Cfg - Channel Configuration Register

    Reference Manual LDMA - Linked DMA 25.7.23 LDMA_CHx_CFG - Channel Configuration Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions DSTINCSIGN Destination Address Increment Sign...
  • Page 842: Ldma_Chx_Loop - Channel Loop Counter Register

    Reference Manual LDMA - Linked DMA 25.7.24 LDMA_CHx_LOOP - Channel Loop Counter Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions LOOPCNT...
  • Page 843: Ldma_Chx_Ctrl - Channel Descriptor Control Word Register

    Reference Manual LDMA - Linked DMA 25.7.25 LDMA_CHx_CTRL - Channel Descriptor Control Word Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description DSTMODE Destination Addressing Mode This field specifies the destination addressing mode of linked descriptors. After loading a linked descriptor, reading this field will indicate the destination addressing mode of the linked descriptor.
  • Page 844 Reference Manual LDMA - Linked DMA Name Reset Access Description 27:26 SIZE Unit Data Transfer Size This field specifies the size of data transferred. Value Mode Description BYTE Each unit transfer is a byte HALFWORD Each unit transfer is a half-word WORD Each unit transfer is a word 25:24...
  • Page 845 Reference Manual LDMA - Linked DMA Name Reset Access Description UNIT6 Six unit transfers per arbitration UNIT8 Eight unit transfers per arbitration UNIT16 Sixteen unit transfers per arbitration UNIT32 32 unit transfers per arbitration UNIT64 64 unit transfers per arbitration UNIT128 128 unit transfers per arbitration UNIT256...
  • Page 846: Ldma_Chx_Src - Channel Descriptor Source Data Addres

    Reference Manual LDMA - Linked DMA 25.7.26 LDMA_CHx_SRC - Channel Descriptor Source Data Addres... Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:0 SRCADDR Source Data Address Writing to this register sets the source address. Reading from this register during a DMA transfer will indicate the next source read address.
  • Page 847: Ldma_Chx_Link - Channel Descriptor Link Structure Add

    Reference Manual LDMA - Linked DMA 25.7.28 LDMA_CHx_LINK - Channel Descriptor Link Structure Add... Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:2 LINKADDR Link Structure Address To use linking, write the address of the the first linked descriptor to this register. When a linked descriptor is loaded, it may also be linked to another descriptor.
  • Page 848: Register Description

    Reference Manual LDMA - Linked DMA 25.9 Register Description 25.9.1 LDMAXBAR_CHx_REQSEL - Channel Peripheral Request Select Reg... Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 21:16...
  • Page 849: Wdog - Watch Dog Timer

    Reference Manual WDOG - Watch Dog Timer 26. WDOG - Watch Dog Timer Quick Facts What? The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can be enabled in all energy modes as long as the low frequency clock source is available.
  • Page 850: Clock Source

    Reference Manual WDOG - Watch Dog Timer 26.3.1 Clock Source Four clock sources are available for use with the watchdog, through the CLKSEL field in CMU_WDOGn_CFG. The selected oscillator source automatically starts when the watchdog is enabled. To prevent accidental change of the clock selection, CMU_WDOGLOCK can be written anything other than UNLOCK code.
  • Page 851: Window Interrupt

    Reference Manual WDOG - Watch Dog Timer 26.3.5 Window Interrupt This interrupt occurs when the watchdog is cleared below a certain threshold. This threshold is given by the formula: (PERSEL+3) = [2 + 1]*WARNSEL / 8 / f WINDOW where f is the frequency of the selected clock. This value will be approximately 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, or 87.5% of the timeout value based on the WINSEL field of the WDOGn_CFG.
  • Page 852: Prs As Watchdog Clear

    Reference Manual WDOG - Watch Dog Timer 26.3.6 PRS as Watchdog Clear A PRS channel (selected by register PRS_CONSUMER_WDOGn_SRC0) can be used to clear the watchdog counter. To enable this feature, CLRSRC must be set to 1. Figure 26.2 PRS Clearing WDOG on page 852 shows how the PRS channel takes over the WDOG clear function.
  • Page 853: Register Map

    Reference Manual WDOG - Watch Dog Timer 26.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 WDOG_IPVERSION IP Version Register 0x004 WDOG_EN RW ENABLE Enable Register 0x008 WDOG_CFG RW CONFIG Configuration Register 0x00C WDOG_CMD...
  • Page 854: Register Description

    Reference Manual WDOG - Watch Dog Timer Offset Name Type Description 0x3024 WDOG_SYNCBUSY_TGL Synchronization Busy Register 26.5 Register Description 26.5.1 WDOG_IPVERSION - IP Version Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version The read only IPVERSION field gives the version for this module.
  • Page 855: Wdog_Cfg - Configuration Register

    Reference Manual WDOG - Watch Dog Timer 26.5.3 WDOG_CFG - Configuration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 30:28 WINSEL...
  • Page 856 Reference Manual WDOG - Watch Dog Timer Name Reset Access Description Value Mode Description SEL0 Timeout period of 9 wdog cycles SEL1 Timeout period of 17 wdog cycles SEL2 Timeout period of 33 wdog cycles SEL3 Timeout period of 65 wdog cycles SEL4 Timeout period of 129 wdog cycles SEL5...
  • Page 857 Reference Manual WDOG - Watch Dog Timer Name Reset Access Description Set to disallow EM4 entry by software. Value Mode Description DISABLE EM4 can be entered by software. See EMU for detailed descrip- tion. ENABLE EM4 cannot be entered by software. EM3RUN EM3 Run Set to keep WDOG running in EM3.
  • Page 858: Wdog_Cmd - Command Register

    Reference Manual WDOG - Watch Dog Timer 26.5.4 WDOG_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions CLEAR WDOG Timer Clear...
  • Page 859: Wdog_If - Interrupt Flag Register

    Reference Manual WDOG - Watch Dog Timer 26.5.6 WDOG_IF - Interrupt Flag Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PEM1...
  • Page 860: Wdog_Ien - Interrupt Enable Register

    Reference Manual WDOG - Watch Dog Timer 26.5.7 WDOG_IEN - Interrupt Enable Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions PEM1...
  • Page 861: Wdog_Lock - Lock Register

    Reference Manual WDOG - Watch Dog Timer 26.5.8 WDOG_LOCK - Lock Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Con- ventions 15:0 LOCKKEY...
  • Page 862: Revision History

    Reference Manual Revision History 27. Revision History Revision 0.4 April, 2019 • First version for public release. • Updated front page and figures. • Updated SE chapter. • Added access mode "H" to registers that are modified by hardware. • Added descriptions to bit fields missing descriptions. •...
  • Page 863: Appendix 1. Abbreviations

    Reference Manual Abbreviations Appendix 1. Abbreviations This section lists abbreviations used in this document. Table 1.1. Abbreviations Abbreviation Description Analog to Digital Converter Advanced Encryption Standard Automatic Frequency Control Automatic Gain Control AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architec- ture".
  • Page 864 Reference Manual Abbreviations Abbreviation Description Detection of Signal Arrival DSSS Direct Sequence Spread Spectrum Electronic Code Book (AES mode of operation) EFM32 Energy Friendly Microcontroller EFR32 Wireless Gecko Energy Mode Energy Management Unit Forward Error Correction Finite Impulse Response Frame Controller Frequency Shift Keying GFSK Gaussian Frequency Shift Keying...
  • Page 865 Reference Manual Abbreviations Abbreviation Description Peripheral Reflex System Pulse Width Modulation Radio Controller Random Access Memory Radio Frequency Reset Management Unit Radio State Machine RSSI Received Signal Strength Indicator Real Time Counter Receive Radio Sequencer Serial Peripheral Interface Sample Rate Converter STIMER Sequencer Timer Software...
  • Page 866 Trademark Information Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®...

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