Cmu_Hfpresc - High Frequency Clock Prescaler Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.5.32 CMU_HFPRESC - High Frequency Clock Prescaler Register

Offset
0x100
Reset
Access
Name
Bit Name
31:25 Reserved
24:24 HFCLKLEPRESC
Specifies the clock divider for HFCLKLE.
Value
0
1
23:13 Reserved
12:8 PRESC
Specifies the clock divider for HFCLK (relative to HFSRCCLK).
Value
PRESC
7:0 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW HFCLKLE Prescaler
Mode Description
DIV2 HFCLKLE is HFBUSCLK
DIV4 HFCLKLE is HFBUSCLK
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x00 RW HFCLK Prescaler
Description
Clock division factor of PRESC+1.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Bit Position
divided by 2.
LE
divided by 4.
LE
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
1.2 Conven-
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