Idac_Dutyconfig - Duty Cycle Configuration Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

27.5.3 IDAC_DUTYCONFIG - Duty Cycle Configuration Register

Offset
0x00C
Reset
Access
Name
Bit Name
31:2 Reserved
1 EM2DUTYCYCLE-
DIS
Set to disable duty cycling in EM2.
0 Reserved
27.5.4 IDAC_STATUS - Status Register
Offset
0x018
Reset
Access
Name
Bit Name
31:2 Reserved
1 APORTCONFLICT
1 if any of the APORT BUSes being requested by the IDAC are also being requested by another peripheral
0 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Duty Cycle Enable
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 R APORT Conflict Output
To ensure compatibility with future devices, always write bits to 0. More information in
tions
IDAC - Current Digital to Analog Converter
Bit Position
Bit Position
Reference Manual
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
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