Emu_Dcdcctrl - Dcdc Control - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

10.5.15 EMU_DCDCCTRL - DCDC Control

Offset
0x040
Reset
Access
Name
Bit Name
31:6 Reserved
5 DCDCMODEEM4
Determines the DCDC mode in EM4H. This bit is ignored if DCDCMODE=Bypass. Reset with POR, Hard Pin Reset, or
BOD Reset.
Value
0
1
4 DCDCMODEEM23
Determines the DCDC mode in EM2 and EM3. This bit is ignored if DCDCMODE=Bypass. Reset with POR, Hard Pin Re-
set, or BOD Reset.
Value
0
1
3:2 Reserved
1:0 DCDCMODE
Determines the operating mode of the DCDC regulator. Reset with POR, Hard Pin Reset, or BOD Reset.
Value
0
1
2
3
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
1 RW DCDC Mode EM4H
Mode Description
EM4SW DCDC mode is according to DCDCMODE field.
EM4LOWPOWER DCDC mode is low power.
1 RW DCDC Mode EM23
Mode Description
EM23SW DCDC mode is according to DCDCMODE field.
EM23LOWPOWER DCDC mode is low power.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x3 RW Regulator Mode
Mode Description
BYPASS DCDC regulator is operating in bypass mode. Prior to configuring
DCDCMODE=BYPASS, software must set EMU_DCDCCLIMCTRL.BY-
PLIMEN=1 to prevent excessive current between VREGVDD and
DVDD supplies.
LOWNOISE DCDC regulator is operating in low noise mode.
LOWPOWER DCDC regulator is operating in low power mode.
OFF DCDC regulator is off and the bypass switch is off. Note: DVDD must
be supplied externally
Bit Position
Reference Manual
EMU - Energy Management Unit
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 256