Msc_Readctrl - Read Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

7.5.2 MSC_READCTRL - Read Control Register

Offset
0x004
Reset
Access
Name
Bit Name
31:29 Reserved
28 SCBTP
Enable suppressed Conditional Branch Target Prefetch (SCBTP) function. SCBTP saves energy by delaying Cortex-M con-
ditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction rea-
ches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of
both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is
saved for each branch not taken, with a negligible performance penalty.
27:26 Reserved
25:24 MODE
After reset, the core clock is 19 MHz from the HFRCO and the MODE field of MSC_READCTRL register is set to WS1. The
reset value is WS1 because the HFRCO may produce a frequency above 19 MHz before it is calibrated. A large wait states
is associated with high frequency. When changing to a higher frequency, this register must be set to a large wait states first
before the core clock is switched to the higher frequency. When changing to a lower frequency, this register should be set
to lower wait states after the frequency transition has been completed. If the HFRCO is used as clock source, wait until the
oscillator is stable on the new frequency to avoid unpredictable behavior.See Flash Wait-States table for the corresponding
threshold for different wait-states.
Value
0
1
2
3
23:10 Reserved
9 USEHPROT
Use ahb_hrpot to determine if the instruction is cacheable or not
8 PREFETCH
Set to configure level of prefetching.
7:6 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Suppress Conditional Branch Target Perfetch
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x1 RWH Read Mode
Mode Description
WS0 Zero wait-states inserted in fetch or read transfers
WS1 One wait-state inserted for each fetch or read transfer. See Flash Wait-
States table for details
WS2 Two wait-states inserted for eatch fetch or read transfer. See Flash
Wait-States table for details
WS3 Three wait-states inserted for eatch fetch or read transfer. See Flash
Wait-States table for details
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW AHB_HPROT Mode
1 RW Prefetch Mode
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Bit Position
Reference Manual
MSC - Memory System Controller
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
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