Register Description; Msc_Ctrl - Memory System Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

7.5 Register Description

7.5.1 MSC_CTRL - Memory System Control Register

Offset
0x000
Reset
Access
Name
Bit Name
31:5 Reserved
4 TIMEOUTFAULTEN
When this bit is set, bus faults are generated when the bus system times out during an access, e.g., when reading a regis-
ter from an LE peripheral that is changing too fast to get a stable value
3 IFCREADCLEAR
This bit controls what happens when an IFC register in a module is read.
Value
0
1
2 PWRUPONDEMAND 0
When set, during wake up, pending AHB transfer will cause MSC to issue power up request to CMU. If not set, will always
issue power up request if PWRUPONCMD is not set either.
1 CLKDISFAULTEN
When this bit is set, busfaults are generated on accesses to peripherals/system devices with clocks disabled
0 ADDRFAULTEN
When this bit is set, busfaults are generated on accesses to unmapped parts of system and code address space
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Timeout Bus Fault Response Enable
0 RW IFC Read Clears IF
Description
IFC register reads 0. No side-effect when reading.
IFC register reads the same value as IF, and the corresponding inter-
rupt flags are cleared.
RW Power Up on Demand During Wake Up
0 RW Clock-disabled Bus Fault Response Enable
1 RW Invalid Address Bus Fault Response Enable
Bit Position
Reference Manual
MSC - Memory System Controller
1.2 Conven-
Rev. 1.1 | 135