Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

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EFR32xG14 Wireless Gecko

Reference Manual

The Wireless Gecko portfolio of SoCs (EFR32) includes Mighty

Gecko (EFR32MG14), Blue Gecko (EFR32BG14), and Flex

Gecko (EFR32FG14) families. With support for Zigbee

Bluetooth Low Energy (BLE) and proprietary protocols, the Wire-

less Gecko portfolio is ideal for enabling energy-friendly wireless

networking for IoT devices.

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup

times, a scalable high-power amplifier, an integrated balun and no-compromise MCU

features.

Core / Memory

ARM Cortex

M4 processor

with DSP extensions, FPU and MPU

Debug Interface

Radio Transceiver

RFSENSE

Sub GHz

LNA

RF Frontend

RFSENSE

2.4 GHz

LNA

RF Frontend

BALUN

Lowest power mode with peripheral operational:

EM0—Active

silabs.com | Building a more connected world.

Flash Program

Memory

RAM Memory

LDMA Controller

DEMOD

PGA

IFADC

To Sub GHz

receive I/Q

AGC

mixers and PA

Frequency

MOD

Synthesizer

To 2.4 GHz receive

To Sub GHz

I/Q mixers and PA

and 2.4 GHz PA

EM1—Sleep

EM2—Deep Sleep

, Thread,

Clock Management

H-F Crystal

H-F

Oscillator

RC Oscillator

Regulator

Auxiliary H-F RC

L-F

Oscillator

RC Oscillator

Converter

L-F Crystal

Ultra L-F RC

Brown-Out

Oscillator

32-bit bus

Peripheral Reflex System

Serial

I/O Ports

Interfaces

External

USART

Interrupts

Low Energy

General

UART

Purpose I/O

Pin Reset

Pin Wakeup

EM3—Stop

KEY FEATURES

• 32-bit ARM® Cortex-M4 core with 40 MHz

maximum operating frequency

• Scalable Memory and Radio configuration

options available in several footprint

compatible QFN packages

• 12-channel Peripheral Reflex System

enabling autonomous interaction of MCU

peripherals

• Autonomous Hardware Crypto Accelerator

and True Random Number Generator

• Integrated balun for 2.4 GHz and

integrated PA with up to 19 dBm transmit

power for 2.4 GHz and 20 dBm transmit

power for Sub-GHz radios

• Integrated DC-DC with RF noise mitigation

Energy Management

Other

Voltage

CRYPTO

Voltage Monitor

CRC

DC-DC

Power-On Reset

True Random

Number Generator

Detector

SMU

Timers and Triggers

Analog I/F

Timer/Counter

Protocol Timer

Low Energy

Comparator

Timer

Sensor Interface

Pulse Counter

Watchdog Timer

Real Time

Counter and

Cryotimer

Calendar

EM4—Hibernate

EM4—Shutoff

ADC

Analog

IDAC

VDAC

Op-Amp

Rev. 1.1

Table of Contents

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Summary of Contents for Silicon Laboratories EFR32xG14 Wireless Gecko

Page 1 EFR32xG14 Wireless Gecko Reference Manual The Wireless Gecko portfolio of SoCs (EFR32) includes Mighty Gecko (EFR32MG14), Blue Gecko (EFR32BG14), and Flex KEY FEATURES ® Gecko (EFR32FG14) families. With support for Zigbee , Thread, • 32-bit ARM® Cortex-M4 core with 40 MHz...
Page 2: Table Of Contents
Table of Contents 1. About This Document ......1.1 Introduction.......26 1.2 Conventions .
Page 3 4.3.1 Writing ......52 4.3.2 Reading ......54 4.3.3 FREEZE Register .
Page 4 4.7.41 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 ...92 4.7.42 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 ...93 4.7.43 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0 .
Page 5 6.5.9 AAP_IDR - AAP Identification Register ....124 7. MSC - Memory System Controller ..... . 125 7.1 Introduction.
Page 6 8.3 Functional Description ......156 8.3.1 Channel Descriptor ......156 8.3.2 Channel Configuration .
Page 7 9.2 Features....... 199 9.3 Functional Description ......200 9.3.1 Reset Levels .
Page 8 10.5.5 EMU_CMD - Command Register ....243 10.5.6 EMU_EM4CTRL - EM4 Control Register ....244 10.5.7 EMU_TEMPLIMITS - Temperature Limits for Interrupt Generation .
Page 9 11.3.9 Interrupts ......304 11.3.10 Wake-up ......305 11.3.11 Protection .
Page 10 11.5.42 CMU_FREEZE - Freeze Register ....357 11.5.43 CMU_PCNTCTRL - PCNT Control Register ....358 11.5.44 CMU_ADCCTRL - ADC Control Register .
Page 11 13.5.8 RTCC_IFS - Interrupt Flag Set Register ....394 13.5.9 RTCC_IFC - Interrupt Flag Clear Register ....395 13.5.10 RTCC_IEN - Interrupt Enable Register .
Page 12 15.3.6 Example ......425 15.4 Register Map......425 15.5 Register Description .
Page 13 16.5.16 PCNTn_OVSCFG - Oversampling Config Register (Async Reg) ..477 17. I2C - Inter-Integrated Circuit Interface ..... 478 17.1 Introduction .
Page 14 18.3.1 Modes of Operation ......529 18.3.2 Asynchronous Operation..... . . 529 18.3.3 Synchronous Operation .
Page 15 19.2 Features ......616 19.3 Functional Description ......617 19.3.1 Frame Format .
Page 16 20.3.6 GPIO Input/Output ......673 20.4 Register Map......674 20.5 Register Description .
Page 17 21.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) ..733 21.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) ..733 21.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) ..734 21.5.9 LETIMERn_IF - Interrupt Flag Register .
Page 18 23.3.13 Sine Generation Mode ..... . . 760 23.3.14 Interrupt Flags ......760 23.3.15 PRS Outputs .
Page 19 25.3 Functional Description ......814 25.3.1 Power Supply ......814 25.3.2 Warm-up Time .
Page 20 26.3.14 EM2 Deep Sleep or EM3 Stop Operation ....868 26.3.15 ASYNC ADC_CLK Usage Restrictions and Benefits ... . . 869 26.3.16 Window Compare Function .
Page 21 27.3.6 Minimizing Output Transition ..... 922 27.3.7 Duty Cycle Configuration..... . . 922 27.3.8 Calibration .
Page 22 28.5.9 LESENSE_CHEN - Channel Enable Register (Async Reg) ... 967 28.5.10 LESENSE_SCANRES - Scan Result Register (Async Reg) ..968 28.5.11 LESENSE_STATUS - Status Register (Async Reg) ... . . 969 28.5.12 LESENSE_PTR - Result Buffer Pointers (Async Reg) .
Page 23 30.2 Features ......1011 30.3 Functional Description ......1012 30.3.1 Built-In Tests .
Page 24 31.6.9 CRYPTO_SEQCTRL - Sequence Control ....1061 31.6.10 CRYPTO_SEQCTRLB - Sequence Control B ....1062 31.6.11 CRYPTO_IF - AES Interrupt Flags .
Page 25 32.1 Introduction ......1082 32.2 Features ......1083 32.3 Functional Description .
Page 26: About This Document
Reference Manual About This Document 1. About This Document 1.1 Introduction This document contains reference material for the EFR32 devices. All modules and peripherals in the EFR32 devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such differences, including pinout, are covered in the device data sheets and applicable errata documents.
Page 27: Related Documentation
Reference Manual About This Document 0x prefix is used for hexadecimal numbers 0b prefix is used for binary numbers Numbers without prefix are in decimal representation. Reserved Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the Register Description.
Page 28: System Overview
Reference Manual System Overview 2. System Overview Quick Facts What? The EFR32 Wireless Gecko is a highly integrated, configurable and low power wireless System-on- Chip (SoC) with a robust set of MCU and radio pe- ripherals. Why? The radio enables support for zigbee, Thread, Blue- tooth Low Energy (BLE) and proprietary protocols in 2.4 GHz and sub-GHz frequency bands while the MCU system allows customized protocols and appli-...
Page 29: Block Diagrams
Reference Manual System Overview 2.2 Block Diagrams The block diagram for the EFR32 System-On-Chip series is shown in (Figure 2.1 EFR32 System-On-Chip Block Diagram on page 29). Core / Memory Clock Management Energy Management Other H-F Crystal Voltage CRYPTO Voltage Monitor Oscillator RC Oscillator Regulator...
Page 30: Mcu Features Overview
Reference Manual System Overview 2.3 MCU Features Overview • ARMCortex-M4 CPU platform • High Performance 32-bit processor @ up to 40 MHz • Memory Protection Unit • Wake-up Interrupt Controller • Flexible Energy Management System • 5 Energy Modes from EM0 to EM4 provide flexibility between higher performance and low power •...
Page 31 Reference Manual System Overview • 16+16+32 bit Protocol Timer • 16-bit Pulse Counter • Asynchronous pulse counting/quadrature decoding • 2 Watchdog Timers with dedicated RC oscillator • Ultra Low Power Precision Analog Peripherals • 12-bit 1 Msamples/s Analog to Digital Converter •...
Page 32: Oscillators And Clocks
Reference Manual System Overview 2.4 Oscillators and Clocks EFR32 has six different oscillators integrated, as shown in Table 2.1 EFR32 Oscillators on page Table 2.1. EFR32 Oscillators Oscillator Frequency Optional? External Description components HFXO 38 MHz - 40 MHz Crystal High accuracy, low jitter high frequency crystal oscillator.
Page 33: Transmit Mode
Reference Manual System Overview 2.7 Transmit Mode In transmit mode EFR32 performs the following functionality: • Automatic PA power ramping during the start and end of a frame transmit • Programmable output power • Optional preamble and synchronization word insertion •...
Page 34: Hardware Crc Support
Reference Manual System Overview 2.12 Hardware CRC Support EFR32 supports a configurable CRC generation in transmit and verification in receive mode: • 8, 16, 24 or 32 bit CRC value • Configurable polynomial and initialization value • Optional inversion of CRC value over air •...
Page 35: Data Encryption And Authentication
Reference Manual System Overview 2.15 Data Encryption and Authentication EFR32 has hardware support for AES encryption, decryption and authentication modes. These security operations can be performed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits. AES modes of operations directly supported by the EFR32 hardware are listed in Table 2.2 AES Modes of Operation With Hardware Support on page...
Page 36: Timers
Reference Manual System Overview 2.16 Timers EFR32 includes multiple timers, as can be seen from Table 2.3 EFR32 Timers Overview on page Table 2.3. EFR32 Timers Overview Timer Number of instances Typical clock source Overview RTCC 1 (2) Low frequency (LFXO or 32 bit Real Time Counter and LFRCO) Calendar, typically used to ena-...
Page 37: System Processor
Reference Manual System Processor 3. System Processor Quick Facts What? The industry leading Cortex-M4 processor from ARM is the CPU in the EFR32 devices. Why? The ARM Cortex-M4 is designed for exceptionally short response time, high code density, and high 32- bit throughput while maintaining a strict cost and CM4 Core power consumption budget.
Page 38: Features
Reference Manual System Processor 3.2 Features • Harvard architecture • Separate data and program memory buses (No memory bottleneck as in a single bus system) • 3-stage pipeline • Thumb-2 instruction set • Enhanced levels of performance, energy efficiency, and code density •...
Page 39: Interrupt Operation
Reference Manual System Processor 3.3.1 Interrupt Operation Module Cortex-M NVIC IFS[n] IFC[n] IEN[n] SETENA[n]/CLRENA[n] Active interrupt Interrupt clear Interrupt request IF[n] condition clear SETPEND[n]/CLRPEND[n] Software generated interrupt Figure 3.1. Interrupt Operation The interrupt request (IRQ) lines are connected to the Cortex-M4. Each of these lines (shown in Table 3.1 Interrupt Request Lines (IRQ) on page 40) is connected to one or more interrupt flags in one or more modules.
Page 40: Interrupt Request Lines (Irq)
Reference Manual System Processor 3.3.2 Interrupt Request Lines (IRQ) Table 3.1. Interrupt Request Lines (IRQ) IRQ # Source(s) WDOG0 WDOG1 LDMA GPIO_EVEN TIMER0 USART0_RX USART0_TX ACMP0 ACMP1 ADC0 IDAC0 I2C0 GPIO_ODD TIMER1 USART1_RX USART1_TX LEUART0 PCNT0 CRYPTO0 LETIMER0 RTCC CRYOTIMER FPUEH WTIMER0 VDAC0...
Page 41: Memory And Bus System
Reference Manual Memory and Bus System 4. Memory and Bus System Quick Facts What? A low latency memory system including low energy Flash and RAM with data retention which makes the energy modes attractive. Why? RAM retention reduces the need for storing data in Flash and enables frequent use of the ultra low en- ergy modes EM2 Deep Sleep and EM3 Stop.
Page 42: Introduction
Reference Manual Memory and Bus System 4.1 Introduction The EFR32 contains an AMBA AHB Bus system to allow bus masters to access the memory mapped address space. A multilayer AHB bus matrix connects the 5 master bus interfaces to the AHB slaves (Figure 4.1 EFR32 Bus System on page 42).
Page 43: Functional Description
Reference Manual Memory and Bus System 4.2 Functional Description The memory segments are mapped together with the internal segments of the Cortex-M4 into the system memory map shown by Fig- ure 4.2 System Address Space With Core and Code Space Listing on page Figure 4.2.
Page 44 Reference Manual Memory and Bus System Figure 4.3. System Address Space With Peripheral Listing The embedded SRAM is located at address 0x20000000 in the memory map of the EFR32. When running code located in SRAM start- ing at this address, the Cortex-M4 uses the System bus interface to fetch instructions. This results in reduced performance as the Cor- tex-M4 accesses stack, other data in SRAM and peripherals using the System bus interface.
Page 45: Peripheral Non-Word Access Behavior
Reference Manual Memory and Bus System 4.2.1 Peripheral Non-Word Access Behavior When writing to peripheral registers, all accesses are treated as 32-bit accesses. This means that writes to a register need to be large enough to cover all bits of register, otherwise, any uncovered bits may become corrupted from the partial-word transfer. Thus, the safest practice is to always do 32-bit writes to peripheral registers.
Page 46: Peripheral Bit Set And Clear
Reference Manual Memory and Bus System 4.2.3 Peripheral Bit Set and Clear The EFR32 supports bit set and bit clear access to all peripherals except those listed in Table 4.1 Peripherals that Do Not Support Bit Set and Bit Clear on page 46.
Page 47: Peripherals
Reference Manual Memory and Bus System 4.2.4 Peripherals The peripherals are mapped into the peripheral memory segment, each with a fixed size address range according to Table 4.2 Periph- erals on page Table 4.3 Low Energy Peripherals on page 47 , and Table 4.4 Core Peripherals on page Table 4.2.
Page 48: Bus Matrix
Reference Manual Memory and Bus System Address Range Module Name 0x400E2000 - 0x400E3000 LDMA 0x400E1000 - 0x400E1400 FPUEH 0x400E0000 - 0x400E0800 4.2.5 Bus Matrix The Bus Matrix connects the memory segments to the bus masters as detailed in Introduction. 4.2.5.1 Arbitration The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency, while starvation of simultane- ous accesses to the same bus slave are eliminated.
Page 49 Reference Manual Memory and Bus System 4.2.5.2.1 WS0 Mode In general, when accessing a peripheral, the latency in number of HFCLK cycles, not including master arbitration, is given by: ∙ f , best-case write accesses bus cycles slave cycles HFCLK PERCLK ∙...
Page 50 Reference Manual Memory and Bus System 4.2.5.2.2 WS1 Mode In general, when accessing a peripheral, the latency in number of HFCLK cycles, not including master arbitration, is given by: ∙ f + 2, best-case write accesses bus cycles slave cycles HFCLK PERCLK ∙...
Page 51: Access To Low Energy Peripherals (Asynchronous Registers)
Reference Manual Memory and Bus System 4.2.5.3 Bus Faults System accesses from the core can receive a bus fault in the following condition(s): • The core attempts to access an address that is not assigned to any peripheral or other system device. These faults can be enabled or disabled by setting the ADDRFAULTEN bit appropriately in MSC_CTRL.
Page 52: Writing
Reference Manual Memory and Bus System 4.3.1 Writing Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation. There are two different synchronization mechanisms on the EFR32, immediate synchronization, and delayed synchronization.
Page 53 Reference Manual Memory and Bus System 4.3.1.1 Delayed Synchronization After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corre- sponding busy flag in the <module_name>_SYNCBUSY register (e.g. LETIMER_SYNCBUSY) is set. This flag is set as long as syn- chronization is in progress and is cleared upon completion.
Page 54: Reading
Reference Manual Memory and Bus System 4.3.2 Reading When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates in the Low Energy clock domain or High Frequency clock domain. See Figure 4.13 Read Operation From Low Energy Peripherals on page 54 for an overview of the reading operation.
Page 55: Sram
Reference Manual Memory and Bus System 4.5 SRAM The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and the DMA may be set up to transfer data between the SRAM, Flash and peripherals. •...
Page 56: Di Page Entry Map
Reference Manual Memory and Bus System 4.6 DI Page Entry Map The DI page contains production calibration data as well as device identification information. See the peripheral chapters for how each calibration value is to be used with the associated peripheral. The offset address is relative to the start address of the DI page (see 7.3 Functional Description).
Page 57 Reference Manual Memory and Bus System Offset Name Type Description 0x144 VMONCAL1 VMON Calibration Register 1 0x148 VMONCAL2 VMON Calibration Register 2 0x158 IDAC0CAL0 IDAC0 Calibration Register 0 0x15C IDAC0CAL1 IDAC0 Calibration Register 1 0x168 DCDCLNVCTRL0 DCDC Low-noise VREF Trim Register 0 0x16C DCDCLPVCTRL0 DCDC Low-power VREF Trim Register 0...
Page 58: Di Page Entry Description
Reference Manual Memory and Bus System 4.7 DI Page Entry Description 4.7.1 CAL - CRC of DI-page and calibration temperature Offset Bit Position 0x000 Access Name Name Access Description 31:24 Reserved Reserved for future use 23:16 TEMP Calibration temperature as an usigned int in DegC (25 = 25DegC) 15:0 CRC of DI-page (CRC-16-CCITT)
Page 59: Extinfo - External Component Description
Reference Manual Memory and Bus System 4.7.2 EXTINFO - External Component description Offset Bit Position 0x020 Access Name Name Access Description 31:24 Reserved Reserved for future use 23:16 MCM Revision Value Mode Description REV1 Revision 1 NONE No external component present 15:8 CONNECTION Connection protocal to external interface...
Page 60: Eui48L - Eui48 Oui And Unique Identifier
Reference Manual Memory and Bus System 4.7.3 EUI48L - EUI48 OUI and Unique identifier Offset Bit Position 0x028 Access Name Name Access Description 31:24 OUI48L Lower Octet of EUI48 Organizationally Unique Identifier 23:0 UNIQUEID Unique identifier 4.7.4 EUI48H - OUI Offset Bit Position 0x02C...
Page 61: Meminfo - Flash Page Size And Misc. Chip Information
Reference Manual Memory and Bus System 4.7.6 MEMINFO - Flash page size and misc. chip information Offset Bit Position 0x034 Access Name Name Access Description 31:24 FLASH_PAGE_SIZE Flash page size in bytes coded as 2 ^ ((MEM_IN- FO_PAGE_SIZE + 10) & 0xFF). Ie. the value 0xFF = 512 bytes. 23:16 PINCOUNT Device pin count as unsigned integer (eg.
Page 62: Uniquel - Low 32 Bits Of Device Unique Number
Reference Manual Memory and Bus System 4.7.7 UNIQUEL - Low 32 bits of device unique number Offset Bit Position 0x040 Access Name Name Access Description 31:0 UNIQUEL Low 32 bits of device unique number 4.7.8 UNIQUEH - High 32 bits of device unique number Offset Bit Position 0x044...
Page 63: Part - Part Description
Reference Manual Memory and Bus System 4.7.10 PART - Part description Offset Bit Position 0x04C Access Name Name Access Description 31:24 PROD_REV Production revision as unsigned integer 23:16 DEVICE_FAMILY Device Family Value Mode Description EFR32MG1P EFR32 Mighty Gecko Family Series 1 Device Config 1 EFR32MG1B EFR32 Mighty Gecko Family Series 1 Device Config 1 EFR32MG1V...
Page 64 Reference Manual Memory and Bus System Name Access Description EFR32BG13V EFR32 Blue Gecko Family Series 1 Device Config 3 EFR32FG13P EFR32 Flex Gecko Family Series 1 Device Config 3 EFR32FG13B EFR32 Flex Gecko Family Series 1 Device Config 3 EFR32FG13V EFR32 Flex Gecko Family Series 1 Device Config 3 EFR32MG14P EFR32 Mighty Gecko Family Series 1 Device Config 4...
Page 65: Devinforev - Device Information
Reference Manual Memory and Bus System Name Access Description 15:0 DEVICE_NUMBER Part number as unsigned integer (e.g. 233 for EFR32BG1P233F256GM48-B0) 4.7.11 DEVINFOREV - Device information page revision Offset Bit Position 0x050 Access Name Name Access Description 31:8 Reserved Reserved for future use DEVINFOREV DEVINFO layout revision as unsigned integer (initially 1) 4.7.12 EMUTEMP - EMU Temperature Calibration Information...
Page 66: Adc0Cal0 - Adc0 Calibration Register 0
Reference Manual Memory and Bus System 4.7.13 ADC0CAL0 - ADC0 calibration register 0 Offset Bit Position 0x060 Access Name Name Access Description Reserved Reserved for future use 30:24 GAIN2V5 Gain for 2.5V reference 23:20 NEGSEOFFSET2V5 Negative single ended offset for 2.5V reference 19:16 OFFSET2V5 Offset for 2.5V reference...
Page 67: Adc0Cal1 - Adc0 Calibration Register 1
Reference Manual Memory and Bus System 4.7.14 ADC0CAL1 - ADC0 calibration register 1 Offset Bit Position 0x064 Access Name Name Access Description Reserved Reserved for future use 30:24 GAIN5VDIFF Gain for for 5V differential reference 23:20 NEGSEOFFSET5VDIFF Negative single ended offset with for 5V differential reference 19:16 OFFSET5VDIFF Offset for 5V differential reference...
Page 68: Adc0Cal2 - Adc0 Calibration Register 2
Reference Manual Memory and Bus System 4.7.15 ADC0CAL2 - ADC0 calibration register 2 Offset Bit Position 0x068 Access Name Name Access Description Reserved Reserved for future use 30:24 Reserved Reserved for future use 23:20 Reserved Reserved for future use 19:16 Reserved Reserved for future use 15:8...
Page 69: Hfrcocal0 - Hfrco Calibration Register (4 Mhz)
Reference Manual Memory and Bus System 4.7.17 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) Offset Bit Position 0x080 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 70: Hfrcocal3 - Hfrco Calibration Register (7 Mhz)
Reference Manual Memory and Bus System 4.7.18 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) Offset Bit Position 0x08C Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 71: Hfrcocal6 - Hfrco Calibration Register (13 Mhz)
Reference Manual Memory and Bus System 4.7.19 HFRCOCAL6 - HFRCO Calibration Register (13 MHz) Offset Bit Position 0x098 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 72: Hfrcocal7 - Hfrco Calibration Register (16 Mhz)
Reference Manual Memory and Bus System 4.7.20 HFRCOCAL7 - HFRCO Calibration Register (16 MHz) Offset Bit Position 0x09C Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 73: Hfrcocal8 - Hfrco Calibration Register (19 Mhz)
Reference Manual Memory and Bus System 4.7.21 HFRCOCAL8 - HFRCO Calibration Register (19 MHz) Offset Bit Position 0x0A0 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 74: Hfrcocal10 - Hfrco Calibration Register (26 Mhz)
Reference Manual Memory and Bus System 4.7.22 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) Offset Bit Position 0x0A8 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 75: Hfrcocal11 - Hfrco Calibration Register (32 Mhz)
Reference Manual Memory and Bus System 4.7.23 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) Offset Bit Position 0x0AC Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 76: Hfrcocal12 - Hfrco Calibration Register (38 Mhz)
Reference Manual Memory and Bus System 4.7.24 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) Offset Bit Position 0x0B0 Access Name Name Access Description 31:28 VREFTC HFRCO Temperature Coefficient Trim on Comparator Reference FINETUNINGEN HFRCO enable reference for fine tuning 26:25 CLKDIV HFRCO Clock Output Divide LDOHP...
Page 77: Auxhfrcocal0 - Auxhfrco Calibration Register (4 Mhz)
Reference Manual Memory and Bus System 4.7.25 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) Offset Bit Position 0x0E0 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 78: Auxhfrcocal3 - Auxhfrco Calibration Register (7 Mhz)
Reference Manual Memory and Bus System 4.7.26 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) Offset Bit Position 0x0EC Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 79: Auxhfrcocal6 - Auxhfrco Calibration Register (13 Mhz)
Reference Manual Memory and Bus System 4.7.27 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz) Offset Bit Position 0x0F8 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 80: Auxhfrcocal7 - Auxhfrco Calibration Register (16 Mhz)
Reference Manual Memory and Bus System 4.7.28 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz) Offset Bit Position 0x0FC Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 81: Auxhfrcocal8 - Auxhfrco Calibration Register (19 Mhz)
Reference Manual Memory and Bus System 4.7.29 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz) Offset Bit Position 0x100 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 82: Auxhfrcocal10 - Auxhfrco Calibration Register (26 Mhz)
Reference Manual Memory and Bus System 4.7.30 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz) Offset Bit Position 0x108 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 83: Auxhfrcocal11 - Auxhfrco Calibration Register (32 Mhz)
Reference Manual Memory and Bus System 4.7.31 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz) Offset Bit Position 0x10C Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 84: Auxhfrcocal12 - Auxhfrco Calibration Register (38 Mhz)
Reference Manual Memory and Bus System 4.7.32 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz) Offset Bit Position 0x110 Access Name Name Access Description 31:28 VREFTC AUXHFRCO Temperature Coefficient Trim on Comparator Ref- erence FINETUNINGEN AUXHFRCO enable reference for fine tuning 26:25 CLKDIV AUXHFRCO Clock Output Divide...
Page 85: Vmoncal0 - Vmon Calibration Register 0
Reference Manual Memory and Bus System 4.7.33 VMONCAL0 - VMON Calibration Register 0 Offset Bit Position 0x140 Access Name Name Access Description 31:28 ALTAVDD2V98THRESCOARSE ALTAVDD 2.98 V Coarse Threshold Adjust 27:24 ALTAVDD2V98THRESFINE ALTAVDD 2.98 V Fine Threshold Adjust 23:20 ALTAVDD1V86THRESCOARSE ALTAVDD 1.86 V Coarse Threshold Adjust 19:16 ALTAVDD1V86THRESFINE...
Page 86: Vmoncal1 - Vmon Calibration Register 1
Reference Manual Memory and Bus System 4.7.34 VMONCAL1 - VMON Calibration Register 1 Offset Bit Position 0x144 Access Name Name Access Description 31:28 IO02V98THRESCOARSE IO0 2.98 V Coarse Threshold Adjust 27:24 IO02V98THRESFINE IO0 2.98 V Fine Threshold Adjust 23:20 IO01V86THRESCOARSE IO0 1.86 V Coarse Threshold Adjust 19:16 IO01V86THRESFINE...
Page 87: Vmoncal2 - Vmon Calibration Register 2
Reference Manual Memory and Bus System 4.7.35 VMONCAL2 - VMON Calibration Register 2 Offset Bit Position 0x148 Access Name Name Access Description 31:28 FVDD2V98THRESCOARSE FVDD 2.98 V Coarse Threshold Adjust 27:24 FVDD2V98THRESFINE FVDD 2.98 V Fine Threshold Adjust 23:20 FVDD1V86THRESCOARSE FVDD 1.86 V Coarse Threshold Adjust 19:16 FVDD1V86THRESFINE...
Page 88: Idac0Cal0 - Idac0 Calibration Register 0
Reference Manual Memory and Bus System 4.7.36 IDAC0CAL0 - IDAC0 Calibration Register 0 Offset Bit Position 0x158 Access Name Name Access Description 31:24 SOURCERANGE3TUNING Calibrated middle step (16) of current source mode range 3 23:16 SOURCERANGE2TUNING Calibrated middle step (16) of current source mode range 2 15:8 SOURCERANGE1TUNING Calibrated middle step (16) of current source mode range 1...
Page 89: Idac0Cal1 - Idac0 Calibration Register 1
Reference Manual Memory and Bus System 4.7.37 IDAC0CAL1 - IDAC0 Calibration Register 1 Offset Bit Position 0x15C Access Name Name Access Description 31:24 SINKRANGE3TUNING Calibrated middle step (16) of current sink mode range 3 23:16 SINKRANGE2TUNING Calibrated middle step (16) of current sink mode range 2 15:8 SINKRANGE1TUNING Calibrated middle step (16) of current sink mode range 1...
Page 90: Dcdclpvctrl0 - Dcdc Low-Power Vref Trim Register 0
Reference Manual Memory and Bus System 4.7.39 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 Offset Bit Position 0x16C Access Name Name Access Description 31:24 1V8LPATT0LPCMPBIAS1 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=1 23:16 1V2LPATT0LPCMPBIAS1 DCDC LPVREF Trim for 1.2V output, LPATT=0, LPCMPBIAS=1 15:8 1V8LPATT0LPCMPBIAS0 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=0...
Page 91: Dcdclpvctrl1 - Dcdc Low-Power Vref Trim Register 1
Reference Manual Memory and Bus System 4.7.40 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 Offset Bit Position 0x170 Access Name Name Access Description 31:24 1V8LPATT0LPCMPBIAS3 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=3 23:16 1V2LPATT0LPCMPBIAS3 DCDC LPVREF Trim for 1.2V output, LPATT=0, LPCMPBIAS=3 15:8 1V8LPATT0LPCMPBIAS2 DCDC LPVREF Trim for 1.8V output, LPATT=0, LPCMPBIAS=2...
Page 92: Dcdclpvctrl2 - Dcdc Low-Power Vref Trim Register 2
Reference Manual Memory and Bus System 4.7.41 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 Offset Bit Position 0x174 Access Name Name Access Description 31:24 3V0LPATT1LPCMPBIAS1 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=1 23:16 1V8LPATT1LPCMPBIAS1 DCDC LPVREF Trim for 1.8V output, LPATT=1, LPCMPBIAS=1 15:8 3V0LPATT1LPCMPBIAS0 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=0...
Page 93: Dcdclpvctrl3 - Dcdc Low-Power Vref Trim Register 3
Reference Manual Memory and Bus System 4.7.42 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 Offset Bit Position 0x178 Access Name Name Access Description 31:24 3V0LPATT1LPCMPBIAS3 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=3 23:16 1V8LPATT1LPCMPBIAS3 DCDC LPVREF Trim for 1.8V output, LPATT=1, LPCMPBIAS=3 15:8 3V0LPATT1LPCMPBIAS2 DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=3...
Page 94: Dcdclpcmphyssel1 - Dcdc Lpcmphyssel Trim Register 1
Reference Manual Memory and Bus System 4.7.44 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 Offset Bit Position 0x180 Access Name Name Access Description 31:24 LPCMPHYSSELLPCMPBIAS3 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=3 23:16 LPCMPHYSSELLPCMPBIAS2 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=2 15:8 LPCMPHYSSELLPCMPBIAS1 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=1 LPCMPHYSSELLPCMPBIAS0 DCDC LPCMPHYSSEL Trim, LPCMPBIAS=0 silabs.com | Building a more connected world.
Page 95: Vdac0Maincal - Vdac0 Cals For Main Path
Reference Manual Memory and Bus System 4.7.45 VDAC0MAINCAL - VDAC0 Cals for Main Path Offset Bit Position 0x184 Access Name Name Access Description 31:30 Reserved Reserved for future use 29:24 GAINERRTRIMVDDANAEXTPIN Gain Error Trim Value for DAC main output using references VDDANA and EXTPIN 23:18 GAINERRTRIM2V5...
Page 96: Vdac0Altcal - Vdac0 Cals For Alternate Path
Reference Manual Memory and Bus System 4.7.46 VDAC0ALTCAL - VDAC0 Cals for Alternate Path Offset Bit Position 0x188 Access Name Name Access Description 31:30 Reserved Reserved for future use 29:24 GAINERRTRIMVDDANAEXTPI- Gain Error Trim Value for DAC alternative output using referen- NALT ces VDDANA and EXTPIN 23:18...
Page 97: Vdac0Ch1Cal - Vdac0 Ch1 Error Cal
Reference Manual Memory and Bus System 4.7.47 VDAC0CH1CAL - VDAC0 CH1 Error Cal Offset Bit Position 0x18C Access Name Name Access Description 31:12 Reserved Reserved for future use 11:8 GAINERRTRIMCH1B Gain Error Trim Value for Channel 1 for references 2V5LN, 2V5 GAINERRTRIMCH1A Gain Error Trim Value for Channel 1 for references 1V25LN, 1V25, VDDANA, EXTPIN...
Page 98: Opa0Cal0 - Opa0 Calibration Register For Drivestrength 0, Incbw=1
Reference Manual Memory and Bus System 4.7.48 OPA0CAL0 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 Offset Bit Position 0x190 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 99: Opa0Cal1 - Opa0 Calibration Register For Drivestrength 1, Incbw=1
Reference Manual Memory and Bus System 4.7.49 OPA0CAL1 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 Offset Bit Position 0x194 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 100: Opa0Cal2 - Opa0 Calibration Register For Drivestrength 2, Incbw=1
Reference Manual Memory and Bus System 4.7.50 OPA0CAL2 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 Offset Bit Position 0x198 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 101: Opa0Cal3 - Opa0 Calibration Register For Drivestrength 3, Incbw=1
Reference Manual Memory and Bus System 4.7.51 OPA0CAL3 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 Offset Bit Position 0x19C Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 102: Opa1Cal0 - Opa1 Calibration Register For Drivestrength 0, Incbw=1
Reference Manual Memory and Bus System 4.7.52 OPA1CAL0 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 Offset Bit Position 0x1A0 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 103: Opa1Cal1 - Opa1 Calibration Register For Drivestrength 1, Incbw=1
Reference Manual Memory and Bus System 4.7.53 OPA1CAL1 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 Offset Bit Position 0x1A4 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 104: Opa1Cal2 - Opa1 Calibration Register For Drivestrength 2, Incbw=1
Reference Manual Memory and Bus System 4.7.54 OPA1CAL2 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 Offset Bit Position 0x1A8 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 105: Opa1Cal3 - Opa1 Calibration Register For Drivestrength 3, Incbw=1
Reference Manual Memory and Bus System 4.7.55 OPA1CAL3 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 Offset Bit Position 0x1AC Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 106: Opa0Cal4 - Opa0 Calibration Register For Drivestrength 0, Incbw=0
Reference Manual Memory and Bus System 4.7.56 OPA0CAL4 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 Offset Bit Position 0x1D0 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 107: Opa0Cal5 - Opa0 Calibration Register For Drivestrength 1, Incbw=0
Reference Manual Memory and Bus System 4.7.57 OPA0CAL5 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 Offset Bit Position 0x1D4 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 108: Opa0Cal6 - Opa0 Calibration Register For Drivestrength 2, Incbw=0
Reference Manual Memory and Bus System 4.7.58 OPA0CAL6 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 Offset Bit Position 0x1D8 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 109: Opa0Cal7 - Opa0 Calibration Register For Drivestrength 3, Incbw=0
Reference Manual Memory and Bus System 4.7.59 OPA0CAL7 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 Offset Bit Position 0x1DC Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 110: Opa1Cal4 - Opa1 Calibration Register For Drivestrength 0, Incbw=0
Reference Manual Memory and Bus System 4.7.60 OPA1CAL4 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 Offset Bit Position 0x1E0 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 111: Opa1Cal5 - Opa1 Calibration Register For Drivestrength 1, Incbw=0
Reference Manual Memory and Bus System 4.7.61 OPA1CAL5 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 Offset Bit Position 0x1E4 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 112: Opa1Cal6 - Opa1 Calibration Register For Drivestrength 2, Incbw=0
Reference Manual Memory and Bus System 4.7.62 OPA1CAL6 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 Offset Bit Position 0x1E8 Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 113: Opa1Cal7 - Opa1 Calibration Register For Drivestrength 3, Incbw=0
Reference Manual Memory and Bus System 4.7.63 OPA1CAL7 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 Offset Bit Position 0x1EC Access Name Name Access Description Reserved Reserved for future use 30:26 OFFSETN OPA Inverting Input Offset Configuration Value. Reserved Reserved for future use 24:20 OFFSETP OPA Non-Inverting Input Offset Configuration Value.
Page 114: Radio Transceiver
Reference Manual Radio Transceiver 5. Radio Transceiver Quick Facts What? The Radio Transceiver provides access to transmit and receive data, radio settings and control inter- face. Why? The Radio Transceiver enables the user to commu- nicate using a wide range of data rates, modulation and frame formats.
Page 115: Introduction
Reference Manual Radio Transceiver 5.1 Introduction The Radio Transceiver of the EFR32 enables the user to control a wide range of settings and options for tailoring radio operation pre- cisely to the users need. It provides access to the transmit and receive data buffers and supports both dynamic and static frame lengths, as well as automatic address filtering and CRC insertion/verification.
Page 116: Dbg - Debug Interface
Reference Manual DBG - Debug Interface 6. DBG - Debug Interface Quick Facts What? The Debug Interface is used to program and debug EFR32 devices. Why? The Debug Interface makes it easy to re-program and update the system in the field, and allows de- bugging with minimal I/O pin usage.
Page 117: Debug Pins
Reference Manual DBG - Debug Interface 6.3.1 Debug Pins The following pins are the debug connections for the device: • Serial Wire Clock Input and Test Clock Input (SWCLKTCK) : This pin is enabled after power-up and has a built-in pull down. •...
Page 118: Debug Lock
Reference Manual DBG - Debug Interface 6.3.3.5 User Flash Page CRC The CRCREQ command initiates a CRC calculation on a given Flash Page. The CRC is only available on the Main, User Data, and Lock Bit pages. It is highly recommended that the system bus is stalled before any CRCREQ commands are issued. The CRC calcula- tion uses the on chip CRC block configured in 32 bit CRC mode.
Page 119: Debugger Reads Of Actionable Registers
Reference Manual DBG - Debug Interface 6.3.6 Debugger Reads of Actionable Registers Some peripheral registers cause particular actions when read, e.g FIFOs which pop and IFC registers which clear the IF flags when read. This can cause problems when debugging and the user wants to read the value without triggering the read action. For this rea- son, by default, the peripherals will not execute these triggered actions when an attached debugger is performing the read accesses through the AAP.
Page 120: Register Description
Reference Manual DBG - Debug Interface 6.5 Register Description 6.5.1 AAP_CMD - Command Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SYSRESETREQ...
Page 121: Aap_Status - Status Register
Reference Manual DBG - Debug Interface 6.5.3 AAP_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LOCKED AAP Locked...
Page 122: Aap_Crccmd - Crc Command Register
Reference Manual DBG - Debug Interface 6.5.5 AAP_CRCCMD - CRC Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CRCREQ CRC Request...
Page 123: Aap_Crcaddr - Crc Address Register
Reference Manual DBG - Debug Interface 6.5.7 AAP_CRCADDR - CRC Address Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:0 CRCADDR 0x00000000 Starting Page Address for CRC Execution Set this to the address the CRC executes on. 6.5.8 AAP_CRCRESULT - CRC Result Register Offset Bit Position...
Page 124: Aap_Idr - Aap Identification Register
Reference Manual DBG - Debug Interface 6.5.9 AAP_IDR - AAP Identification Register Offset Bit Position 0x0FC Reset Access Name Name Reset Access Description 31:0 0x26E60011 AAP Identification Register Access port identification register in compliance with the ARM ADI v5 specification (JEDEC Manufacturer ID) . silabs.com | Building a more connected world.
Page 125: Msc - Memory System Controller
Reference Manual MSC - Memory System Controller 7. MSC - Memory System Controller Quick Facts What? The user can perform Flash memory read, read con- figuration and write operations through the Memory System Controller (MSC) . Why? 01000101011011100110010101110010 The MSC allows the application code, user data and flash lock bits to be stored in non-volatile Flash 01100111011110010010000001001101 memory.
Page 126: Features
Reference Manual MSC - Memory System Controller 7.2 Features • AHB read interface • Scalable access performance to optimize the Cortex-M4 code interface • Zero wait-state access up to 26 MHz • Advanced energy optimization functionality • Conditional branch target prefetch suppression •...
Page 127: Functional Description
Reference Manual MSC - Memory System Controller 7.3 Functional Description The size of the main block is device dependent. The largest size available is 256 KB (128 pages). The information block has 2 KB available for user data. The information block also contains chip configuration data located in a reserved area. The main block is map- ped to address 0x00000000 and the information block is mapped to address 0x0FE00000.
Page 128: Lock Bits (Lb)
Reference Manual MSC - Memory System Controller 7.3.2 Lock Bits (LB) Page Description This page contains the following information: • Main block Page Lock Words (PLWs) • User data page Lock Word (ULWs) • Debug Lock Word (DLW) • Mass erase Lock Word (MLW) •...
Page 129: Bootloader
Reference Manual MSC - Memory System Controller 7.3.4 Bootloader The memory space includes an area for custom-programmed bootloaders. The available bootloader area is for this device family. By default, the system is configured to boot directly into user software after system reset, and there is not a pre-programmed bootloader in the device.
Page 130: Flash Startup
Reference Manual MSC - Memory System Controller 7.3.7 Flash Startup On transitions from EM2/3 to EM0, the flash must be powered up. The time this takes depends on the current operating conditions. To have a deterministic startup-time, set STDLY0 in MSC_STARTUP to 0x64 and clear STDLY1, ASTWAIT, STWSEN and STWS. This will result in a 10 us delay before the flash is ready.
Page 131: Suppressed Conditional Branch Target Prefetch (Scbtp)
Reference Manual MSC - Memory System Controller 7.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP) MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex-M4 conditional branch target prefetches. Normally, the Cortex-M4 core prefetches both the next sequential instruction and the instruction at the branch target ad- dress when a conditional branch instruction reaches the pipeline decode stage.
Page 132: Instruction Cache
Reference Manual MSC - Memory System Controller 7.3.11 Instruction Cache The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled by default, but can be disabled by setting IFCDIS in MSC_READCTRL. When enabled, the instruction cache typically reduces the number of flash reads significantly, thus saving energy.
Page 133: Low Voltage Flash Read
Reference Manual MSC - Memory System Controller the interrupt routine. So, for example, if a cached function is called from the interrupt routine, the instructions for that function will be taken from the cache. The cache content is not retained in EM2, EM3 and EM4. The cache is therefore invalidated regardless of the setting of AIDIS in MSC_READCTRL when entering these energy modes.
Page 134: Register Map
Reference Manual MSC - Memory System Controller 7.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_CTRL Memory System Control Register 0x004 MSC_READCTRL Read Control Register 0x008 MSC_WRITECTRL Write Control Register 0x00C MSC_WRITECMD Write Command Register...
Page 135: Register Description
Reference Manual MSC - Memory System Controller 7.5 Register Description 7.5.1 MSC_CTRL - Memory System Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TIMEOUTFAULTEN...
Page 136: Msc_Readctrl - Read Control Register
Reference Manual MSC - Memory System Controller 7.5.2 MSC_READCTRL - Read Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCBTP...
Page 137: Msc_Writectrl - Write Control Register
Reference Manual MSC - Memory System Controller Name Reset Access Description ICCDIS Interrupt Context Cache Disable Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context. Cache lookup will still be performed in interrupt context. When set, the performance counters will not count when these types of fetches occur. AIDIS Automatic Invalidate Disable When this bit is set the cache is not automatically invalidated when a write or page erase is performed.
Page 138: Msc_Writecmd - Write Command Register
Reference Manual MSC - Memory System Controller 7.5.4 MSC_WRITECMD - Write Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLEARWDATA...
Page 139: Msc_Addrb - Page Erase/Write Address Buffer
Reference Manual MSC - Memory System Controller 7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:0 ADDRB 0x00000000 Page Erase or Write Address Buffer This register holds the page address for the erase or write operation. This register is loaded into the internal MSC_ADDR register when the LADDRIM field in MSC_WRITECMD is set.
Page 140: Msc_Status - Status Register
Reference Manual MSC - Memory System Controller 7.5.7 MSC_STATUS - Status Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:28 PWRUPCKBDFAIL- Flash Power Up Checkerboard Pattern Check Fail Count COUNT This field tells how many times checkboard pattern check fail occured after a reset sequence. 27:24 WDATAVALID Write Data Buffer Valid Flag...
Page 141: Msc_If - Interrupt Flag Register
Reference Manual MSC - Memory System Controller 7.5.8 MSC_IF - Interrupt Flag Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LVEWRITE...
Page 142: Msc_Ifs - Interrupt Flag Set Register
Reference Manual MSC - Memory System Controller 7.5.9 MSC_IFS - Interrupt Flag Set Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LVEWRITE...
Page 143: Msc_Ifc - Interrupt Flag Clear Register
Reference Manual MSC - Memory System Controller 7.5.10 MSC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LVEWRITE...
Page 144: Msc_Ien - Interrupt Enable Register
Reference Manual MSC - Memory System Controller 7.5.11 MSC_IEN - Interrupt Enable Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LVEWRITE...
Page 145: Msc_Lock - Configuration Lock Register
Reference Manual MSC - Memory System Controller 7.5.12 MSC_LOCK - Configuration Lock Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
Page 146: Msc_Cachecmd - Flash Cache Command Register
Reference Manual MSC - Memory System Controller 7.5.13 MSC_CACHECMD - Flash Cache Command Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions STOPPC...
Page 147: Msc_Cachemisses - Cache Misses Performance Counter
Reference Manual MSC - Memory System Controller 7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:0...
Page 148: Msc_Masslock - Mass Erase Lock Register
Reference Manual MSC - Memory System Controller 7.5.16 MSC_MASSLOCK - Mass Erase Lock Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
Page 149: Msc_Startup - Startup Control
Reference Manual MSC - Memory System Controller 7.5.17 MSC_STARTUP - Startup Control Offset Bit Position 0x05C Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 STWS...
Page 150: Msc_Cmd - Command Register
Reference Manual MSC - Memory System Controller 7.5.18 MSC_CMD - Command Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PWRUP Flash Power Up Command...
Page 151: Msc_Aapunlockcmd - Software Unlock Aap Command Register
Reference Manual MSC - Memory System Controller 7.5.20 MSC_AAPUNLOCKCMD - Software Unlock AAP Command Register Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions UNLOCKAAP...
Page 152: Msc_Cacheconfig0 - Cache Configuration Register 0
Reference Manual MSC - Memory System Controller 7.5.21 MSC_CACHECONFIG0 - Cache Configuration Register 0 Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CACHELPLEVEL...
Page 153: Ldma - Linked Dma Controller
Reference Manual LDMA - Linked DMA Controller 8. LDMA - Linked DMA Controller Quick Facts What? The LDMA controller can move data without CPU in- tervention, effectively reducing the energy consump- tion for a data transfer. Why? The LDMA can perform data transfers more energy efficiently than the CPU and allows autonomous op- Flash eration in low energy modes.
Page 154: Features
Reference Manual LDMA - Linked DMA Controller 8.1.1 Features • Flexible Source and Destination transfers • Memory-to-memory • Memory-to-peripheral • Peripheral-to-memory • Peripheral-to-peripheral • DMA transfers triggered by peripherals, software, or linked list • Single or multiple data transfers for each peripheral or software request •...
Page 155: Block Diagram
Reference Manual LDMA - Linked DMA Controller 8.2 Block Diagram An overview of the LDMA and the modules it interacts with is shown in Figure 8.1 LDMA Block Diagram on page 155. Cortex Interrupts LDMA Core Error Channel done Channel 0 Peripheral Channel 1 Peripheral...
Page 156: Functional Description
Reference Manual LDMA - Linked DMA Controller 8.3 Functional Description The Linked DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data.
Page 157 Reference Manual LDMA - Linked DMA Controller 8.3.1.3 Block Size The block size defines the amount of data transferred in one arbitration. It consists of one or more DMA transfers. See 8.3.6.1 Arbitra- tion Priority for more details. 8.3.1.4 Transfer Count The descriptor transfer count defines how many DMA transfers to perform.
Page 158 Reference Manual LDMA - Linked DMA Controller 8.3.1.8 Byte Swap Enabling byte swap reverses the endianness of the incoming source data read into the LDMA’s FIFO. Byte swap is only valid for trans- fer sizes of word and half-word. Note that linked structure reads are not byte swapped. B3b7 B3b0 B2b7...
Page 159 Reference Manual LDMA - Linked DMA Controller 8.3.1.9 DMA Size and Source/Destination Increment Programming The DMA channels’ SIZE, SRCINC, and DSTINC bit-fields are programmed to best utilize memory resources. They provide a means for memory packing and unpacking, as well as for matching the size of data being transmitted to or received from an IO peripheral. The following figure shows how 32-bit words of data are read from a memory source into the DMA’s internal transfer FIFO, and then written out to the memory destination.
Page 160 Reference Manual LDMA - Linked DMA Controller Memory Memory source source 0x200 0x200 First read transmit data= First read transmit data= DMA Controller FIFO DMA Controller FIFO destination destination 0x400 0x400 First write transmit data= First write transmit data= size[1:0] = HALF size[1:0] = HALF src_inc[1:0] = WORD src_inc[1:0] = HALF...
Page 161: Channel Configuration
Reference Manual LDMA - Linked DMA Controller 8.3.2 Channel Configuration Each DMA channel has associated configuration and loop counter registers for controlling direction of address increment , arbitration slots, and descriptor looping. 8.3.2.1 Address Increment/Decrement Normally DMA transfers increment the source and destination addresses after each DMA transfer. Each channel is also capable of dec- rementing the source and/or destination addresses after each DMA transfer.
Page 162: Managing Transfer Errors
Reference Manual LDMA - Linked DMA Controller 8.3.4.1 Peripheral Transfer Requests By default peripherals issue a Single Request (SREQ) when any data is present. For peripherals with a data buffer or FIFO this occurs any time the FIFO is not empty. Upon receiving an SREQ the LDMA will perform one DMA transfer and stop till another request is made.
Page 163 Reference Manual LDMA - Linked DMA Controller Table 8.1. Arbitration Slot Order Arbslot order Arbslot1 Arbslot2 Arbslot4 Arbslot8 The top row shows the order at which the arbitration slots are executed. The remaining part of the table shows a more visual interpreta- tion of the arbitration order.
Page 164 Reference Manual LDMA - Linked DMA Controller 8.3.6.2 DMA Transfer Arbitration In addition to the inter channel arbitration, software can configure when the controller arbitrates during a DMA transfer. This provides reduced latency to higher priority channels when configuring low priority transfers with more arbitration cycles. The LDMA provides four bits that configure how many DMA transfers occur before it re-arbitrates.
Page 165: Channel Descriptor Data Structure
Reference Manual LDMA - Linked DMA Controller 8.3.7 Channel Descriptor Data Structure Each channel descriptor consists of four 32-bit words: • CTRL - control word contains information like transfer count and block size. • SRC - source address points to where to copy data from •...
Page 166 Reference Manual LDMA - Linked DMA Controller 8.3.7.2 SYNC Descriptor Structure This descriptor defines an intra-channel synchronizing structure. It allows the channel to wait for some external stimulus before continu- ing on to the next descriptor. This structure is also used to provide stimulus to another channel to indicate that it may continue. For example channel 1 may be configured to transfer a header into a buffer while channel 2 is simultaneously transferring data into the same structure.
Page 167: Interaction With The Emu
Reference Manual LDMA - Linked DMA Controller Name Description This bit-field serves as the SYNCTRIG match value. A sync match triggers the load of the next linked DMA structure as specified by link_mode, when: (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN). 8.3.7.3 WRI Descriptor Structure This descriptor defines a write-immediate structure.
Page 168: Interrupts
Reference Manual LDMA - Linked DMA Controller 8.3.9 Interrupts The LDMA_IF Interrupt flag register contains one DONE bit for each channel and one combined ERROR bit. When enabled, these in- terrupts are available as interrupts to the Cortex-M4 core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the DMA is enabled in the ARM Cortex-M4 core, an interrupt will be made if one or more of the interrupt flags in LDMA_IF and their corre- sponding bits in LDMA_IEN are set.
Page 169: Descriptor Linked List
Reference Manual LDMA - Linked DMA Controller 8.4.2 Descriptor Linked List This example shows how to use a Linked List of descriptors. Each descriptor has a link address which points to the next descriptor in the list. A descriptor may be removed from the Linked list by altering the Link address of the one before it to point to the one after it. Descriptor Linked lists are useful when handling an array of buffers for communication data.
Page 170 Reference Manual LDMA - Linked DMA Controller To start execution of the linked list of descriptors: • Write the absolute address of the first descriptor to the LINKADR field of the LDMA_CH0_LINK register • Set the LINK bit of LDMA_CH0_LINK register. •...
Page 171: Single Descriptor Looped Transfer
Reference Manual LDMA - Linked DMA Controller 8.4.3 Single Descriptor Looped Transfer This example demonstrates how to use looping using a single descriptor. This method allows a single DMA transfer to be repeated a specified number of times. The looping descriptor is stored in memory and reloaded by hardware. After a specified number of iterations, the transfer stops.
Page 172: Descriptor List With Looping
Reference Manual LDMA - Linked DMA Controller 8.4.4 Descriptor List With Looping This example uses a descriptor list in memory with looping over multiple descriptors. This example also uses the looping feature and continues on with the next sequential descriptor after looping completes. The descriptor list in memory is shown in figure Figure 8.7 Descriptor List With Looping on page 172.
Page 173: Simple Inter-Channel Synchronization
Reference Manual LDMA - Linked DMA Controller 8.4.5 Simple Inter-Channel Synchronization The LDMA controller features synchronization structures which allow differing channels and/or hardware events to pause a DMA se- quence, and wait for a synchronizing event to restart it. In this example DMA channel 0 and 1 are tasked with the transfer of different sets of data. Channel 0 has two transfer structures, and channel 1 just one, but channel 0 must wait until channel 1 has completed its transfer before it starts its second transfer structure.
Page 174 Reference Manual LDMA - Linked DMA Controller SYNC[7] STRUCTTYPE=-SYNC STRUCTTYPE=XFER wait SYNCTRIG[7]=1 STRUCTTYPE=XFER C not fetched until sync_trig[7] is set STRUCTTYPE=SYNC STRUCTTYPE=XFER set SYNC[7] Time Figure 8.8. Simple Intra-channel Synchronization Example Both A and Y effectively start at the same time. A finishes earlier, then it links to B, which waits for the SYNCTRIG[7] bit to be set before loading C.
Page 175: Copy
Reference Manual LDMA - Linked DMA Controller 8.4.6 2D Copy The LDMA can easily perform a 2D copy using a descriptor list with looping. This set up is visualized in Figure 8.9 2D Copy on page 175. For an application working with graphics, this would mean the ability to copy a rectangle of a given width and height from one picture to another.
Page 176 Reference Manual LDMA - Linked DMA Controller Because the first descriptor already transferred one row, the number of looping repeats should be the desired height minus two. There- fore, LOOPCNT should be set to HEIGHT minus two before initiating the transfer. This same method is easily extended to copy multiple rectangles by linking descriptors together.
Page 177: Ping-Pong
Reference Manual LDMA - Linked DMA Controller 8.4.7 Ping-Pong Communication peripherals often use ping-pong buffers. Ping-pong buffers allow the CPU to process data in one buffer while a periph- eral transmits or receives data in the other buffer. Both transmit and receive ping-pong buffers are easily implemented using the LDMA. In either case, this requires two descriptors as shown in Figure 8.10 Infinite Ping-Pong Example on page 177.
Page 178: Scatter-Gather
Reference Manual LDMA - Linked DMA Controller continue to the second buffer. The LINK bit should be cleared to zero. Once software has loaded the first buffer, it will use the LINK- LOAD bit to load the first descriptor and transmit the data. The DONIFS need not be set in each descriptor. The DMA will stop and then generate an interrupt at the completion of each descriptor.
Page 179: Register Map
Reference Manual LDMA - Linked DMA Controller 8.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LDMA_CTRL DMA Control Register 0x004 LDMA_STATUS DMA Status Register 0x008 LDMA_SYNC DMA Synchronization Trigger Register (Single-Cycle RMW) 0x020 LDMA_CHEN DMA Channel Enable Register (Single-Cycle RMW)
Page 180: Register Description
Reference Manual LDMA - Linked DMA Controller Offset Name Type Description 0x1E4 LDMA_CH7_DST Channel Descriptor Destination Data Address Register 0x1E8 LDMA_CH7_LINK Channel Descriptor Link Structure Address Register 8.6 Register Description 8.6.1 LDMA_CTRL - DMA Control Register Offset Bit Position 0x000 Reset Access Name...
Page 181: Ldma_Status - Dma Status Register
Reference Manual LDMA - Linked DMA Controller 8.6.2 LDMA_STATUS - DMA Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 28:24...
Page 182: Ldma_Sync - Dma Synchronization Trigger Register (Single-Cycle Rmw)
Reference Manual LDMA - Linked DMA Controller 8.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW) Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SYNCTRIG...
Page 183: Ldma_Chbusy - Dma Channel Busy Register
Reference Manual LDMA - Linked DMA Controller 8.6.5 LDMA_CHBUSY - DMA Channel Busy Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BUSY...
Page 184: Ldma_Dbghalt - Dma Channel Debug Halt Register
Reference Manual LDMA - Linked DMA Controller 8.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DBGHALT...
Page 185: Ldma_Reqdis - Dma Channel Request Disable Register
Reference Manual LDMA - Linked DMA Controller 8.6.9 LDMA_REQDIS - DMA Channel Request Disable Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REQDIS...
Page 186: Ldma_Linkload - Dma Channel Link Load Register
Reference Manual LDMA - Linked DMA Controller 8.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LINKLOAD...
Page 187: Ldma_If - Interrupt Flag Register
Reference Manual LDMA - Linked DMA Controller 8.6.13 LDMA_IF - Interrupt Flag Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description ERROR Transfer Error Interrupt Flag The ERRORIF flag is set when a read or write error occurs. The CHERROR field in the LDMA_STATUS register reflects the number of the channel which had the last error.
Page 188: Ldma_Ifc - Interrupt Flag Clear Register
Reference Manual LDMA - Linked DMA Controller 8.6.15 LDMA_IFC - Interrupt Flag Clear Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description ERROR (R)W1 Clear ERROR Interrupt Flag Write 1 to clear the ERROR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
Page 189: Ldma_Chx_Reqsel - Channel Peripheral Request Select Register
Reference Manual LDMA - Linked DMA Controller 8.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16...
Page 190 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description 0b0000 PRSREQ0 PRSREQ0 0b0001 PRSREQ1 PRSREQ1 SOURCESEL = 0b001000 (ADC0) 0b0000 ADC0SINGLE ADC0SINGLE REQ/SREQ 0b0001 ADC0SCAN ADC0SCAN REQ/SREQ SOURCESEL = 0b001010 (VDAC0) 0b0000 VDAC0CH0 VDAC0CH0 0b0001 VDAC0CH1 VDAC0CH1 SOURCESEL = 0b001100 (USART0) 0b0000...
Page 191 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description SOURCESEL = 0b011010 (WTIMER0) 0b0000 WTIMER0UFOF WTIMER0UFOF 0b0001 WTIMER0CC0 WTIMER0CC0 0b0010 WTIMER0CC1 WTIMER0CC1 0b0011 WTIMER0CC2 WTIMER0CC2 SOURCESEL = 0b110000 (MSC) 0b0000 MSCWDATA MSCWDATA REQ/SREQ SOURCESEL = 0b110001 (CRYPTO0) 0b0000 CRYPTO0DATA0WR CRYPTO0DATA0WR 0b0001...
Page 192: Ldma_Chx_Cfg - Channel Configuration Register
Reference Manual LDMA - Linked DMA Controller 8.6.18 LDMA_CHx_CFG - Channel Configuration Register Offset Bit Position 0x084 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DSTINCSIGN...
Page 193: Ldma_Chx_Loop - Channel Loop Counter Register
Reference Manual LDMA - Linked DMA Controller 8.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LOOPCNT...
Page 194: Ldma_Chx_Ctrl - Channel Descriptor Control Word Register
Reference Manual LDMA - Linked DMA Controller 8.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register Offset Bit Position 0x08C Reset Access Name Name Reset Access Description DSTMODE Destination Addressing Mode This field specifies the destination addressing mode of linked descriptors. After loading a linked descriptor, reading this field will indicate the destination addressing mode of the linked descriptor.
Page 195 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description 27:26 SIZE Unit Data Transfer Size This field specifies the size of data transferred. Value Mode Description BYTE Each unit transfer is a byte HALFWORD Each unit transfer is a half-word WORD Each unit transfer is a word 25:24...
Page 196 Reference Manual LDMA - Linked DMA Controller Name Reset Access Description UNIT8 Eight unit transfers per arbitration UNIT16 Sixteen unit transfers per arbitration UNIT32 32 unit transfers per arbitration UNIT64 64 unit transfers per arbitration UNIT128 128 unit transfers per arbitration UNIT256 256 unit transfers per arbitration UNIT512...
Page 197: Ldma_Chx_Src - Channel Descriptor Source Data Address Register
Reference Manual LDMA - Linked DMA Controller 8.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:0 SRCADDR 0x00000000 Source Data Address Writing to this register sets the source address. Reading from this register during a DMA transfer will indicate the next source read address.
Page 198: Ldma_Chx_Link - Channel Descriptor Link Structure Address Register
Reference Manual LDMA - Linked DMA Controller 8.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:2 LINKADDR 0x00000000 Link Structure Address To use linking, write the address of the the first linked descriptor to this register. When a linked descriptor is loaded, it may also be linked to another descriptor.
Page 199: Rmu - Reset Management Unit
Reference Manual RMU - Reset Management Unit 9. RMU - Reset Management Unit Quick Facts What? The RMU ensures correct reset operation. It is re- sponsible for connecting the different reset sources to the reset lines of the EFR32. Why? A correct reset sequence is needed to ensure safe RESETn and synchronous startup of the EFR32.
Page 200: Functional Description
Reference Manual RMU - Reset Management Unit 9.3 Functional Description The RMU monitors each of the reset sources of the EFR32. If one or more reset sources go active, the RMU applies reset to the EFR32. When the reset sources go inactive the EFR32 starts up. At startup the EFR32 loads the stack pointer and program entry point from memory, and starts execution.
Page 201: Reset Levels
Reference Manual RMU - Reset Management Unit 9.3.1 Reset Levels The reset sources on EFR32 can be divided in two main groups; Hard resets and Soft resets. The soft resets can be configured to be either DISABLED, LIMITED, EXTENDED or FULL. The reset level for soft reset sources is configured in the xxxRMODE bitfields in RMU_CTRL.
Page 202: Rmu_Rstcause Register
Reference Manual RMU - Reset Management Unit 9.3.2 RMU_RSTCAUSE Register Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may investigate this register in order to determine the cause of the reset. The register is cleared upon POR and software write to RMU_CMD_RCCLR.
Page 203: Power-On Reset (Por)
Reference Manual RMU - Reset Management Unit 9.3.3 Power-On Reset (POR) The POR ensures that the EFR32 does not start up before the AVDD supply voltage has reached the threshold voltage VPORthr (roughly 1.2V). Before the POR threshold voltage is reached, the EFR32 is kept in reset state. The operation of the POR is illustrated in Figure 9.2 RMU Power-on Reset Operation on page 203, with the active low POWERONn reset signal.
Page 204: Resetn Pin Reset
Reference Manual RMU - Reset Management Unit 9.3.5 RESETn Pin Reset The pin reset on EFR32 can be configured to be either hard or soft. By default, pin reset is configured as a soft reset source. To config- ure it as a hard reset, clear the PINRESETSOFT bit in CLW0 in the Lock bit page, see 7.3.2 Lock Bits (LB) Page Description for details.
Page 205 Reference Manual RMU - Reset Management Unit 9.3.10.1 Registers With Alternate Reset Alternate Reset for Registers in RMU RMU Reset Levels POR and hard pin reset RMU_CTRL_WDOGRMODE RMU_CTRL_LOCKUPRMODE RMU_CTRL_SYSRMODE RMU_CTRL_PINRMODE RMU_CTRL_RESETSTATE FULL reset RMU_LOCK_LOCKKEY Alternate Reset for Registers in CMU CMU Reset Levels FULL reset CMU_LFRCOCTRL...
Page 206: Register Map
Reference Manual RMU - Reset Management Unit 9.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RMU_CTRL Control Register 0x004 RMU_RSTCAUSE Reset Cause Register 0x008 RMU_CMD Command Register 0x00C RMU_RST Reset Control Register 0x010 RMU_LOCK...
Page 207: Register Description
Reference Manual RMU - Reset Management Unit 9.5 Register Description 9.5.1 RMU_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 25:24...
Page 208 Reference Manual RMU - Reset Management Unit Name Reset Access Description LOCKUPRMODE Core LOCKUP Reset Mode Controls the reset level for Core LOCKUP reset request. Value Mode Description DISABLED Reset request is blocked. LIMITED The CRYOTIMER, DEBUGGER, RTCC, are not reset. EXTENDED The CRYOTIMER, DEBUGGER are not reset.
Page 209: Rmu_Rstcause - Reset Cause Register
Reference Manual RMU - Reset Management Unit 9.5.2 RMU_RSTCAUSE - Reset Cause Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4RST...
Page 210: Rmu_Cmd - Command Register
Reference Manual RMU - Reset Management Unit Name Reset Access Description PORST Power on Reset Set if a power on reset has been performed. Must be cleared by software. See Table 9.2 RMU Reset Cause Register Inter- pretation on page 202 for details on how to interpret this bit.
Page 211: Rmu_Lock - Configuration Lock Register
Reference Manual RMU - Reset Management Unit 9.5.5 RMU_LOCK - Configuration Lock Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
Page 212: Emu - Energy Management Unit
Reference Manual EMU - Energy Management Unit 10. EMU - Energy Management Unit Quick Facts What? The EMU (Energy Management Unit) handles the different low energy modes in EFR32 Why? The need for performance and peripheral functions varies over time in most applications. By efficiently scaling the available resources in real time to match the demands of the application, the energy con- sumption can be kept at a minimum.
Page 213: Features
Reference Manual EMU - Energy Management Unit 10.2 Features The primary features of the EMU are listed below: • Energy Modes control • Entry into EM4 Hibernate or EM4 Shutoff • Configuration of regulators and clocks for each Energy Mode •...
Page 214: Functional Description
Reference Manual EMU - Energy Management Unit 10.3 Functional Description The EMU is responsible for managing the wide range of energy modes available in EFR32. The block works in harmony with the entire platform to easily transition between energy modes in the most efficient manner possible. The following diagram Figure 10.1 EMU Overview on page 214, shows the relative connectivity to the various blocks in the system.
Page 215: Energy Modes
Reference Manual EMU - Energy Management Unit 10.3.1 Energy Modes EFR32 features six main energy modes, referred to as Energy Mode 0 (EM0 Active) through Energy Mode 4 (EM4 Shutoff). The Cor- tex-M4 is only available for program execution in EM0 Active. In EM0 Active/EM1 Sleep any peripheral function can be enabled. EM2 Deep Sleep through EM4 Shutoff, also referred to as low energy modes, provide a significantly reduced energy consumption while still allowing a rich set of peripheral functionality.
Page 216 Reference Manual EMU - Energy Management Unit EM2 Deep EM3 Stop EM4 Hiber- EM4 Shutoff Active/EM1 Sleep nate Sleep RFSENSE (Ultra Low Energy RF Detection) Available Available Available Available Available High Frequency Oscillators (HFRCO, HFXO) and Available Clocks (HFSRCLK, HFCLK, HFCORECLK, HFBUSCLK, HFPERCLK, HFRADIOCLK, HFCLKLE) Auxiliary High Frequency Oscillator (AUXHFR-...
Page 217 Reference Manual EMU - Energy Management Unit EM2 Deep EM3 Stop EM4 Hiber- EM4 Shutoff Active/EM1 Sleep nate Sleep GPIO Pin State Retention Available Available Approximate time. Refer to the data sheet Leaving the debugger connected when in EM2 or EM3 will cause the system to enter a higher power EM2 mode in which the high frequency clocks are still enabled and certain core functionality is still powered-up in order to maintain debug-functionality.
Page 218 Reference Manual EMU - Energy Management Unit 10.3.1.3 EM2 Deep Sleep This is the first level into the low power energy modes. Most of the high frequency peripherals are disabled or have reduced functionali- ty. Memory and registers retain their values. •...
Page 219: Entering Low Energy Modes
Reference Manual EMU - Energy Management Unit 10.3.1.5 EM4 Hibernate The majority of peripherals are shutoff to reduce leakage power. A few selected peripherals are available. System memory and regis- ters do not retain values. GPIO PAD state and RTCC RAM are retained. Wake-up from EM4 Hibernate requires a reset to the system, returning it back to EM0 Active •...
Page 220 Reference Manual EMU - Energy Management Unit 10.3.2.2 Entry Into EM2 Deep Sleep or EM3 Stop Energy mode EM2 Deep Sleep or EM3 Stop may be entered when all of the following conditions are true: • Radio RAC state machine is in OFF state •...
Page 221: Exiting A Low Energy Mode
Reference Manual EMU - Energy Management Unit 10.3.3 Exiting a Low Energy Mode A system in EM2 Deep Sleep and EM3 Stop can be woken up to EM0 Active through regular interrupt requests from active peripherals. Since state and RAM retention is available, the EFR32 is fully restored and can continue to operate as before it went into the Low Ener- gy Mode.
Page 222: Power Configurations
Reference Manual EMU - Energy Management Unit 10.3.4 Power Configurations The EFR32 allows several power configurations with additional options giving flexible power architecture selection. In order to provide the lowest power consuming radio solutions, the EFR32 comes with a DC-DC module to power internal circuits. The DC-DC requires an external inductor and capacitor (refer to the data sheet for recommended values).
Page 223 Reference Manual EMU - Energy Management Unit 10.3.4.1 Power Configuration 0: Unconfigured Upon power-on reset (POR) or entry into EM4 Shutoff, the system is configured in a safe state that supports all of the available Power Configurations. The Unconfigured Configuration is shown in the simplified diagram below. In the Unconfigured Configuration: •...
Page 224 Reference Manual EMU - Energy Management Unit 10.3.4.2 Power Configuration 1: No DC-DC In Power Configuration 1, the DC-DC converter is programmed in Off mode and the Bypass switch is Off. The DVDD pin must be pow- ered externally - typically, DVDD is connected to the main supply. DVDD powers the internal Digital LDO (i.e., REGPWRSEL=1) which powers the digital circuits.
Page 225 Reference Manual EMU - Energy Management Unit 10.3.4.3 Power Configuration 2: DC-DC For the lowest power applications, the DC-DC converter can be used to power the DVDD supply, as well as RFVDD and PAVDD. In Power Configuration 2, the DC-DC Output (V ) is connected to DVDD.
Page 226: Dc-To-Dc Interface
Reference Manual EMU - Energy Management Unit Main Supply – AVDD VREGVDD IOVDD VREGVDD IOVDD AVDD Bypass FLASH Switch DCDC DC-DC Driver VREGSW VREGSW ANASW DC-DC VREGVSS VREGVSS Analog Blocks DVDD DVDD REGPWRSEL Digital Digital Logic Power Analog Amplifier DECOUPLE DECOUPLE PAVDD RFVDD...
Page 227 Reference Manual EMU - Energy Management Unit 10.3.5.1 Bypass Mode In Bypass mode, the VREGVDD input voltage is directly shorted to the DC-DC converter output through an internal switch. Consult the data sheet for the Bypass switch impedance specification. The Bypass Current Limit limits the maximum current drawn from the input supply in Bypass mode. This current limit is enabled by setting the BYPLIMEN bit in the EMU_DCDCCLIMCTRL register, and the limit value may be adjusted between 20 mA and 320 mA using the BYPLIMSEL bitfield in the EMU_DCDCMISCCTRL register.
Page 228: Analog Peripheral Power Selection
Reference Manual EMU - Energy Management Unit 10.3.5.3.2 Low Noise (LN) Discontinuous Conduction Mode (DCM) To enable DCM, the LNFORCECCM bit in EMU_DCDCMISCCTRL must be cleared before entering LN. Typically, this configuration would occur while the part was in Bypass mode. Once DCM is enabled, the DC-DC should operate in DCM at light load currents. How- ever, as the load current increases, the DC-DC will automatically transition into CCM without software intervention.
Page 229: Digital Ldo Power Selection
Reference Manual EMU - Energy Management Unit 10.3.7 Digital LDO Power Selection The digital LDO may be powered from one of two supply pins, depending on the configuration of the REGPWRSEL bit in the EMU_PWRCTRL register. At startup, the digital is powered from the AVDD pin. When powered from AVDD, the LDO current is limited to 20 mA.
Page 230: Voltage Scaling
Reference Manual EMU - Energy Management Unit 10.3.9 Voltage Scaling The voltage scaling feature allows for a tradeoff between power and performance. Voltage scaling applies an adjustment to the supply voltage for the on-chip digital logic and memories. For EM0 and EM1 operation, full device performance is supported when the Voltage Scale Level is set to its highest value.
Page 231 Reference Manual EMU - Energy Management Unit 10.3.9.2 EM23 Voltage Scaling The EM23VSCALE bitfield in EMU_CTRL allows user to independently setup the voltage scaling value for EM23 energy mode. The EM23VSCALE in EMU_CTRL should be programmed to a level which is less than or equal to VSCALE in EMU_STATUS. This means that EM23 voltage scaling is always a voltage scaling down process.
Page 232: Em23 Peripheral Retention Disable
Reference Manual EMU - Energy Management Unit 10.3.10 EM23 Peripheral Retention Disable Peripherals that are available in EM2 Deep Sleep or EM3 Stop can optionally be powered down during EM2 Deep Sleep or EM3 Stop. This allows lower energy consumption in these energy modes. However, when powering down, these peripherals are independently reset so the registers lose their configuration values.
Page 233: Voltage Monitor (Vmon)
Reference Manual EMU - Energy Management Unit 10.3.12 Voltage Monitor (VMON) The EFR32 features an extremely low energy Voltage Monitor (VMON) capable of running down to EM4 Hibernate. Trigger points are preloaded but may be reconfigured. • AVDD X 2 •...
Page 234: Powering Off Sram Blocks
Reference Manual EMU - Energy Management Unit • Using the above numbers and the VMON calibration equations: • T = 35 1.86 • T = 87 2.98 • V = 21.53 mV • V = 1.106 V • Using the VMON threshold equations (with Y=2.2 V), Thres = 51 (rounded from 50.8) and Y = 2.204 V calib...
Page 235: Registers Latched In Em4
Reference Manual EMU - Energy Management Unit 10.3.15 Registers latched in EM4 The following registers will be latched when entering EM4. After wake-up from EM4, these registers will be reset and require reprog- ramming prior to writing the EMU_CMD_EM4UNLATCH command. •...
Page 236: Register Map
Reference Manual EMU - Energy Management Unit 10.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EMU_CTRL Control Register 0x004 EMU_STATUS Status Register 0x008 EMU_LOCK Configuration Lock Register 0x00C EMU_RAM0CTRL Memory Control Register 0x010 EMU_CMD...
Page 237 Reference Manual EMU - Energy Management Unit Offset Name Type Description 0x108 EMU_EM23PERNORETAINCTRL When Set Corresponding Peripherals May Get Powered Down in EM23 silabs.com | Building a more connected world. Rev. 1.1 | 237...
Page 238: Register Description
Reference Manual EMU - Energy Management Unit 10.5 Register Description 10.5.1 EMU_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16...
Page 239 Reference Manual EMU - Energy Management Unit Name Reset Access Description EM01LD Reserved for internal use. Do not change. Reserved for internal use. Do not change. EM2BODDIS Disable BOD in EM2 This bit is used to disable BODs to minimize current in EM2. Reset with POR or Hard Pin Reset EM2BLOCK Energy Mode 2 Block This bit is used to prevent the MCU from entering Energy Mode 2 or 3.
Page 240: Emu_Status - Status Register
Reference Manual EMU - Energy Management Unit 10.5.2 EMU_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TEMPACTIVE Temperature Measurement Active...
Page 241 Reference Manual EMU - Energy Management Unit Name Reset Access Description RESV RESV 15:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions VMONFVDD VMON VDDFLASH Channel Indicates the status of the VDDFLASH channel of the VMON. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 242: Emu_Lock - Configuration Lock Register
Reference Manual EMU - Energy Management Unit 10.5.3 EMU_LOCK - Configuration Lock Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
Page 243: Emu_Cmd - Command Register
Reference Manual EMU - Energy Management Unit 10.5.5 EMU_CMD - Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM01VSCALE2 EM01 Voltage Scale Command to Scale to Voltage Scale Level 2...
Page 244: Emu_Em4Ctrl - Em4 Control Register
Reference Manual EMU - Energy Management Unit 10.5.6 EMU_EM4CTRL - EM4 Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16...
Page 245: Emu_Templimits - Temperature Limits For Interrupt Generation
Reference Manual EMU - Energy Management Unit 10.5.7 EMU_TEMPLIMITS - Temperature Limits for Interrupt Generation Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4WUEN...
Page 246: Emu_If - Interrupt Flag Register
Reference Manual EMU - Energy Management Unit 10.5.9 EMU_IF - Interrupt Flag Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description TEMPHIGH Temperature High Limit Reached Set when the value of a periodic temperature measurement is higher or equal than TEMPHIGH in EMU_TEMPLIMITS TEMPLOW Temperature Low Limit Reached Set when the value of a periodic temperature measurement is lower or equal than TEMPHIGH in EMU_TEMPLIMITS...
Page 247 Reference Manual EMU - Energy Management Unit Name Reset Access Description PFETOVERCUR- PFET Current Limit Hit RENTLIMIT Reserved for internal use. VMONFVDDRISE VMON VDDFLASH Channel Rise A rising edge on VMON VDDFLASH channel has been detected. VMONFVDDFALL VMON VDDFLASH Channel Fall A falling edge on VMON VDDFLASH channel has been detected.
Page 248: Emu_Ifs - Interrupt Flag Set Register
Reference Manual EMU - Energy Management Unit 10.5.10 EMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description TEMPHIGH Set TEMPHIGH Interrupt Flag Write 1 to set the TEMPHIGH interrupt flag TEMPLOW Set TEMPLOW Interrupt Flag Write 1 to set the TEMPLOW interrupt flag TEMP Set TEMP Interrupt Flag...
Page 249 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONFVDDRISE Set VMONFVDDRISE Interrupt Flag Write 1 to set the VMONFVDDRISE interrupt flag VMONFVDDFALL Set VMONFVDDFALL Interrupt Flag Write 1 to set the VMONFVDDFALL interrupt flag 13:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions VMONIO0RISE...
Page 250: Emu_Ifc - Interrupt Flag Clear Register
Reference Manual EMU - Energy Management Unit 10.5.11 EMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description TEMPHIGH (R)W1 Clear TEMPHIGH Interrupt Flag Write 1 to clear the TEMPHIGH interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
Page 251 Reference Manual EMU - Energy Management Unit Name Reset Access Description NFETOVERCUR- (R)W1 Clear NFETOVERCURRENTLIMIT Interrupt Flag RENTLIMIT Write 1 to clear the NFETOVERCURRENTLIMIT interrupt flag. Reading returns the value of the IF and clears the corre- sponding interrupt flags (This feature must be enabled globally in MSC.). PFETOVERCUR- (R)W1 Clear PFETOVERCURRENTLIMIT Interrupt Flag...
Page 252: Emu_Ien - Interrupt Enable Register
Reference Manual EMU - Energy Management Unit 10.5.12 EMU_IEN - Interrupt Enable Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description TEMPHIGH TEMPHIGH Interrupt Enable Enable/disable the TEMPHIGH interrupt TEMPLOW TEMPLOW Interrupt Enable Enable/disable the TEMPLOW interrupt TEMP TEMP Interrupt Enable Enable/disable the TEMP interrupt...
Page 253 Reference Manual EMU - Energy Management Unit Name Reset Access Description VMONFVDDRISE VMONFVDDRISE Interrupt Enable Enable/disable the VMONFVDDRISE interrupt VMONFVDDFALL VMONFVDDFALL Interrupt Enable Enable/disable the VMONFVDDFALL interrupt 13:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions VMONIO0RISE...
Page 254: Emu_Pwrlock - Regulator And Supply Lock Register
Reference Manual EMU - Energy Management Unit 10.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
Page 255: Emu_Pwrctrl - Power Control Register
Reference Manual EMU - Energy Management Unit 10.5.14 EMU_PWRCTRL - Power Control Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions IMMEDIATEPWRS-...
Page 256: Emu_Dcdcctrl - Dcdc Control
Reference Manual EMU - Energy Management Unit 10.5.15 EMU_DCDCCTRL - DCDC Control Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DCDCMODEEM4 DCDC Mode EM4H...
Page 257: Emu_Dcdcmiscctrl - Dcdc Miscellaneous Control Register
Reference Manual EMU - Energy Management Unit 10.5.16 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:28...
Page 258 Reference Manual EMU - Energy Management Unit Name Reset Access Description 11:8 PFETCNT PFET Switch Number Selection Low Noise mode PFET power switch count number. The selected number of switches are PFETCNT+1. Reset with POR, Hard Pin Reset, or BOD Reset. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 259: Emu_Dcdczdetctrl - Dcdc Power Train Nfet Zero Current Detector Control Register
Reference Manual EMU - Energy Management Unit 10.5.17 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ZDETBLANKDLY...
Page 260: Emu_Dcdcclimctrl - Dcdc Power Train Pfet Current Limiter Control Register
Reference Manual EMU - Energy Management Unit 10.5.18 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions BYPLIMEN...
Page 261: Emu_Dcdclncompctrl - Dcdc Low Noise Compensator Control Register
Reference Manual EMU - Energy Management Unit 10.5.19 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:28 COMPENC3 Low Noise Mode Compensator C3 Trim Value LN mode compensator C3 trim, 0.5pF-8pF in 0.5pF steps. Reset with POR, Hard Pin Reset, or BOD Reset. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 262: Emu_Dcdclnvctrl - Dcdc Low Noise Voltage Register
Reference Manual EMU - Energy Management Unit 10.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 14:8...
Page 263: Emu_Dcdclpvctrl - Dcdc Low Power Voltage Register
Reference Manual EMU - Energy Management Unit 10.5.21 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LPVREF...
Page 264: Emu_Dcdclpctrl - Dcdc Low Power Control Register
Reference Manual EMU - Energy Management Unit 10.5.22 EMU_DCDCLPCTRL - DCDC Low Power Control Register Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 26:25...
Page 265: Emu_Dcdclnfreqctrl - Dcdc Low Noise Controller Frequency Control
Reference Manual EMU - Energy Management Unit 10.5.23 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 28:24...
Page 266: Emu_Vmonavddctrl - Vmon Avdd Channel Control
Reference Manual EMU - Energy Management Unit 10.5.25 EMU_VMONAVDDCTRL - VMON AVDD Channel Control Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 23:20...
Page 267: Emu_Vmonaltavddctrl - Alternate Vmon Avdd Channel Control
Reference Manual EMU - Energy Management Unit 10.5.26 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
Page 268: Emu_Vmondvddctrl - Vmon Dvdd Channel Control
Reference Manual EMU - Energy Management Unit 10.5.27 EMU_VMONDVDDCTRL - VMON DVDD Channel Control Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
Page 269: Emu_Vmonio0Ctrl - Vmon Iovdd0 Channel Control
Reference Manual EMU - Energy Management Unit 10.5.28 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control Offset Bit Position 0x09C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
Page 270: Emu_Ram1Ctrl - Memory Control Register
Reference Manual EMU - Energy Management Unit 10.5.29 EMU_RAM1CTRL - Memory Control Register Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RAMPOWERDOWN...
Page 271: Emu_Ram2Ctrl - Memory Control Register
Reference Manual EMU - Energy Management Unit 10.5.30 EMU_RAM2CTRL - Memory Control Register Offset Bit Position 0x0B8 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RAMPOWERDOWN...
Page 272: Emu_Dcdclpem01Cfg - Configuration Bits For Low Power Mode To Be Applied During Em01, This Field Is Only Relevant If Lp Mode Is Used In Em01
Reference Manual EMU - Energy Management Unit 10.5.31 EMU_DCDCLPEM01CFG - Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Rel- evant If LP Mode is Used in EM01 Offset Bit Position 0x0EC Reset Access Name Name Reset...
Page 273: Emu_Em23Pernoretaincmd - Clears Corresponding Bits In Em23Pernoretainsta- Tus Unlocking Access To Peripheral
Reference Manual EMU - Energy Management Unit 10.5.32 EMU_EM23PERNORETAINCMD - Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Pe- ripheral Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LEUART0UNLOCK...
Page 274 Reference Manual EMU - Energy Management Unit Name Reset Access Description ACMP1UNLOCK Clears Status Bit of ACMP1 and Unlocks Access to It clears status bit of ACMP1 and unlocks access to it ACMP0UNLOCK Clears Status Bit of ACMP0 and Unlocks Access to It clears status bit of ACMP0 and unlocks access to it silabs.com | Building a more connected world.
Page 275: Emu_Em23Pernoretainstatus - Status Indicating If Peripherals Were Powered Down In Em23, Subsequently Locking Access To It
Reference Manual EMU - Energy Management Unit 10.5.33 EMU_EM23PERNORETAINSTATUS - Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It Offset Bit Position 0x104 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LEUART0LOCKED...
Page 276 Reference Manual EMU - Energy Management Unit Name Reset Access Description I2C0LOCKED Indicates If I2C0 Powered Down During EM23 Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORE- TAINCMD Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PCNT0LOCKED...
Page 277: Emu_Em23Pernoretainctrl - When Set Corresponding Peripherals May Get Powered Down In Em23
Reference Manual EMU - Energy Management Unit 10.5.34 EMU_EM23PERNORETAINCTRL - When Set Corresponding Peripherals May Get Powered Down in EM23 Offset Bit Position 0x108 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LEUART0DIS...
Page 278 Reference Manual EMU - Energy Management Unit Name Reset Access Description ACMP1DIS Allow Power Down of ACMP1 During EM23 Allow power down of ACMP1 during EM23 ACMP0DIS Allow Power Down of ACMP0 During EM23 Allow power down of ACMP0 during EM23 silabs.com | Building a more connected world.
Page 279: Cmu - Clock Management Unit
Reference Manual CMU - Clock Management Unit 11. CMU - Clock Management Unit Quick Facts What? The CMU controls oscillators and clocks. EFR32 supports 6 different oscillators with minimized power consumption and short start-up time. The CMU has HW support for calibration of RC oscillators. Why? WDOG clock Oscillators and clocks contribute significantly to the...
Page 280: Functional Description
Reference Manual CMU - Clock Management Unit 11.3 Functional Description An overview of the high frequency portion of the CMU is shown in Figure 11.1 CMU Overview - High Frequency Portion on page 280. An overview of the low frequency portion is shown in Figure 11.2 CMU Overview - Low Frequency Portion on page 281.
Page 281: System Clocks
Reference Manual CMU - Clock Management Unit CMU_HFBUSCLKEN0.LE HFBUSCLK Clock HFCLK Gate 50% duty HFCLKLE prescaler (/2, /4) CMU_HFPRESC.HFCLKLEPRESC CMU_LFACLKEN0.LESENSE LFACLK Clock LESENSE prescaler Gate LFXO CMU_LFAPRESC0.LESENSE LFRCO clock CMU_LFACLKEN0.LETIMER0 LFXO Timeout switch ULFRCO LFACLK LFACLK Clock LETIMER0 prescaler Gate CMU_LFACLKSEL.LFA CMU_LFAPRESC0.LETIMER0 LFRCO...
Page 282 Reference Manual CMU - Clock Management Unit 11.3.1.1 HFCLK - High Frequency Clock HFSRCCLK is the selected High Frequency Source Clock. HFCLK is an optionally prescaled version of HFSRCCLK. The HFSRCCLK, and therefore HFCLK, can be driven by a high-frequency oscillator, such as HFRCO or HFXO, or one of the low-frequency oscillators (LFRCO or LFXO).
Page 283 Reference Manual CMU - Clock Management Unit 11.3.1.5 HFRADIOCLK - High Frequency Radio Clock HFRADIOCLK is a prescaled version of HFCLK which drives the High-Frequency Radio Peripherals. All the radio peripherals that are driven by this clock can be clock gated completely when not in use. This is done by clearing the clock enable bit for the specific periph- eral in CMU_HFRADIOCLKEN0.
Page 284: Oscillators
Reference Manual CMU - Clock Management Unit 11.3.1.9 LFECLK - Low Frequency E Clock LFECLK is the selected clock for the Low Energy E Peripherals. There are several selectable sources for LFECLK: LFRCO, LFXO and ULFRCO. In addition, the LFECLK can be disabled, which is the default setting. The selection is configured using the LFE field in CMU_LFECLKSEL.
Page 285 Reference Manual CMU - Clock Management Unit 11.3.2.1 Enabling and Disabling The different oscillators can typically be enabled and disabled via both hardware and software mechanisms. Enabling via software is done by setting the corresponding enable bit in the CMU_OSCENCMD register. Disabling via software is done by setting the corresponding disable bit in CMU_OSCENCMD.
Page 286 Reference Manual CMU - Clock Management Unit 11.3.2.1.1 LFRCO and LFXO The LFXO and LFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. WDOGn can be configured to force the LFXO or LFRCO to become (and remain) enabled when such an oscillator is selected as its clock source via the CLKSEL bitfield in the WDOGn_CTRL register while SWOSCBLOCK is set.
Page 287 Reference Manual CMU - Clock Management Unit check that the LFRCO (or LFXO) is signaled to be ready before allowing or initiating the EM4 entry if that oscillator is required in EM4. Also, to guarantee latching the latest settings, no control write should be ongoing upon EM4 entry as can be checked via the CMU_SYNCBUSY register.
Page 288 Reference Manual CMU - Clock Management Unit 11.3.2.1.5 AUXHFRCO The AUXHFRCO can be enabled and disabled by software via the CMU_OSCENCMD register. The AUXHFRCO is disabled automati- cally when entering EM2, EM3, or EM4. Hardware based AUXHFRCO enabling and disabling is however performed by the ADC mod- ule when AUXCLK is selected for its operation and by the LESENSE module making it available even when being in EM2/EM3.
Page 289 Reference Manual CMU - Clock Management Unit 11.3.2.2 Oscillator Start-up Time and Time-out The start-up time differs per oscillator and the usage of an oscillator clock can further be delayed by a time-out. The LFRCO, LFXO and the HFXO have a configurable time-out which is set by software in the (various) TIMEOUT bitfields of the CMU_LFRCOCTRL, CMU_LFXOCTRL and CMU_HFXOTIMEOUTCTRL registers respectively.
Page 290 Reference Manual CMU - Clock Management Unit 11.3.2.3 Switching Clock Source The HFRCO oscillator is a low energy oscillator with extremely short start-up time. Therefore, this oscillator is always chosen by hard- ware as the clock source for HFCLK when the device starts up (e.g. after reset and after waking up from EM2 Deep Sleep and EM3 Stop).
Page 291 Reference Manual CMU - Clock Management Unit HFXO CMU_CMD.HFCLKSEL CMU_OSCENCMD.HFRCOEN CMU_OSCENCMD.HFRCODIS CMU_OSCENCMD.HFXOEN CMU_OSCENCMD.HFXODIS CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_STATUS.HFRCOSEL CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_STATUS.HFXOSEL HFCLK HFRCO HFXO HFXO time-out period Figure 11.5. CMU Switching from HFRCO to HFXO after HFXO is ready Switching clock source for LFACLK, LFBCLK, and LFECLK is done by setting the LFA, LFB and LFE bitfields in CMU_LFACLKSEL, CMU_LFBCLKSEL and CMU_LFECLKSEL respectively.
Page 292 Reference Manual CMU - Clock Management Unit 11.3.2.4 HFXO Configuration The High Frequency Crystal Oscillator needs to be configured to ensure safe startup for the given crystal. Refer to the device data sheet and application notes for guidelines in selecting correct components and crystals as well as for configuration trade-offs. The HFXO crystal is connected to the HFXTAL_N/HFXTAL_P pins as shown in Figure 11.6 HFXO Pin Connection on page 292 Gecko Device...
Page 293 Reference Manual CMU - Clock Management Unit Reset || EM2/EM3 entry || (CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS) HFXO major mode configuration from CMU->HFXOCTRL: · MODE · LOWPOWER CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN Using Startup state configuration from CMU->HFXOSTARTUPCTRL: · IBTRIMXOCORE · CTUNE · REGISH STARTUP ·...
Page 294 Reference Manual CMU - Clock Management Unit state configuration depending on the crystal's CL, RESR and oscillation frequency. This configuration is programmed into the IBTRIM- XOCORE, REGISH and CTUNE bitfields of the CMU_HFXOSTEADYSTATECTRL register. The minimum duration of the steady phase is configured in the STEADYTIMEOUT bitfield of the CMU_HFXOTIMEOUTCTRL register.
Page 295 Reference Manual CMU - Clock Management Unit 11.3.2.4.1 Automatic HFXO Start The enabling of the HFXO and its selection as HFSRCCLK source can be performed automatically by hardware. Automatic HFXO ena- ble and select can for example be used upon wake-up of the Radio Controller (RAC). Automatic control of the HFXO is controlled via the AUTOSTARTRDYSELRAC, AUTOSTARTSELEM0EM1 and AUTOSTARTEM0EM1 bits in the CMU_HFXOCTRL register.
Page 296 Reference Manual CMU - Clock Management Unit RAC wake-up with CMU_HFXOCTRL.AUTOSTARTRDYSELRAC = 1 EM0/EM1 entry with CMU_HFXOCTRL.AUTOSTARTSELEM0EM1 = 1 HFXO ready Automatic switch to HFXO (and disable of HFRCO) CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_HFCLKSTATUS.HF = HFRCO CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_HFCLKSTATUS.HF = HFXO HFCLK HFRCO HFXO Figure 11.8.
Page 297 Reference Manual CMU - Clock Management Unit EM0/EM1 Entry && CMU_HFXOCTRL.AUTOSTARTSELEM0EM1 = 0 RAC wake-up with CMU_HFXOCTRL.AUTOSTARTRDYSELRAC = 1 HFXO ready Automatic switch to HFXO and disable of HFRCO HFRCO selected CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_HFCLKSTATUS.HF = HFRCO CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_HFCLKSTATUS.HF = HFXO HFCLK HFRCO HFXO...
Page 298 Reference Manual CMU - Clock Management Unit 11.3.2.5 LFXO Configuration The Low Frequency Crystal Oscillator (LFXO) is default configured to ensure safe startup for all crystals. In order to optimize startup time and power consumption for a given crystal, it is possible to adjust the startup gain in the oscillator by programming the GAIN field in CMU_LFXOCTRL.
Page 299 Reference Manual CMU - Clock Management Unit The XTAL oscillation amplitude can be controlled via the HIGHAMPL bitfield in CMU_LFXOCTRL. Setting HIGHAMPL to 1 will result in higher amplitude, which in turn provides safer operation, somewhat improved duty cycle, and lower sensitivity to noise at the cost of increased current consumption.
Page 300 Reference Manual CMU - Clock Management Unit 11.3.2.8 RC Oscillator Calibration The CMU has built-in HW support to efficiently calibrate the RC oscillators (LFRCO, HFRCO, AUXHFRCO, etc) at run-time. For a com- plete list of supported oscillators, refer to DOWNSEL and UPSEL fields in CMU_CALCTRL. See Figure 11.13 HW-support for RC Oscil- lator Calibration on page 300 for an illustration of this circuit.
Page 301 Reference Manual CMU - Clock Management Unit Up-counter sampled and CALRDY interrupt flag set. Sampled value available in CMU_CALCNT. Up-counter Down-counter Calibration Started Calibration Stopped (counters stopped) Figure 11.14. Single Calibration (CONT=0) Up-counter sampled and CALRDY Up-counter sampled and CALRDY interrupt flag set.
Page 302: Configuration For Operating Frequencies
Reference Manual CMU - Clock Management Unit 11.3.3 Configuration for Operating Frequencies The HFXO is capable of frequencies up to 40 MHz, which allows the EFR32 to run at up to this frequency. However the Memory Sys- tem Controller (MSC) and the Low Energy Peripheral Interface need to be configured correctly to allow operation at higher frequencies as explained below.
Page 303: Energy Modes
Reference Manual CMU - Clock Management Unit 11.3.4 Energy Modes The availability of oscillators and system clocks depends on the chosen energy mode. Default the high frequency oscillators (HFRCO, AUXHFRCO, and HFXO) and high frequency clocks (HFSRCLK, HFCLK, HFCORECLK, HFBUSCLK, HFPERCLK, HFRADIOCLK, HFCLKLE) are available downto EM1 Sleep.
Page 304: Clock Output On A Pin
Reference Manual CMU - Clock Management Unit 11.3.5 Clock Output on a Pin It is possible to configure the CMU to output clocks on the CMU_CLK0, CMU_CLK1 and CMU_CLK2 pins. This clock selection is done using the CLKOUTSEL0, CLKOUTSEL1 and CLKOUTSEL2 bitfields respectively in CMU_CTRL. The required output pins must be en- abled in the CMU_ROUTEPEN register and the pin locations can be configured in the CMU_ROUTELOC0 register.
Page 305: Wake-Up
Reference Manual CMU - Clock Management Unit 11.3.10 Wake-up The CMU can be (partially) active all the way down to EM4 Shutoff. It can wake up the CPU from EM2 upon LFRCO or LFXO becoming ready as LFRCORDY and LFXORDY can be used as wake-up interrupt. 11.3.11 Protection It is possible to lock the control- and command registers to prevent unintended software writes to critical clock settings.
Page 306: Register Map
Reference Manual CMU - Clock Management Unit 11.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_CTRL CMU Control Register 0x010 CMU_HFRCOCTRL HFRCO Control Register 0x018 CMU_AUXHFRCOCTRL AUXHFRCO Control Register 0x020 CMU_LFRCOCTRL LFRCO Control Register...
Page 307 Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x114 CMU_HFEXPPRESC High Frequency Export Clock Prescaler Register 0x120 CMU_LFAPRESC0 Low Frequency a Prescaler Register 0 (Async Reg) 0x128 CMU_LFBPRESC0 Low Frequency B Prescaler Register 0 (Async Reg) 0x130 CMU_LFEPRESC0 Low Frequency E Prescaler Register 0 (Async Reg) 0x138...
Page 308: Register Description
Reference Manual CMU - Clock Management Unit 11.5 Register Description 11.5.1 CMU_CTRL - CMU Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions HFRADIOCLKEN...
Page 309 Reference Manual CMU - Clock Management Unit Name Reset Access Description HFXOQ HFXO (qualified) HFSRCCLK HFSRCCLK CLKOUTSEL0 0x00 Clock Output Select 0 Controls the clock output multiplexer. To actually output on the pin, set CLKOUT0PEN in CMU_ROUTE. Value Mode Description DISABLED Disabled ULFRCO...
Page 310: Cmu_Hfrcoctrl - Hfrco Control Register
Reference Manual CMU - Clock Management Unit 11.5.2 CMU_HFRCOCTRL - HFRCO Control Register Write this register to set the frequency band in which the HFRCO is to operate. Always update all fields in this register at once by writ- ing the value for the desired band, which has been obtained from the Device Information page entry for that band. The TUNING, FINE- TUNING, FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a non-precon- figured frequency.
Page 311 Reference Manual CMU - Clock Management Unit even while the system is running on the HFRCO. Only write CMU_HFRCOCTRL when it is ready for an update as indicated by HFRCOBSY=0 in CMU_SYNCBUSY. Offset Bit Position 0x010 Reset Access Name Name Reset Access Description...
Page 312: Cmu_Auxhfrcoctrl - Auxhfrco Control Register
Reference Manual CMU - Clock Management Unit 11.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register Write this register with the production calibrated values from the Device Info pages. The TUNING, FINETUNING, FINETUNINGEN and CLKDIV bitfields can be used to tune a specific band (FREQRANGE) of the oscillator to a non-preconfigured frequency. Only write CMU_AUXHFRCOCTRL when it is ready for an update as indicated by AUXHFRCOBSY=0 in CMU_SYNCBUSY.
Page 313: Cmu_Lfrcoctrl - Lfrco Control Register
Reference Manual CMU - Clock Management Unit 11.5.4 CMU_LFRCOCTRL - LFRCO Control Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:28 GMCCURTUNE Tuning of Gmc Current Set to tune GMC current. This field is updated with the production calibrated value during reset, and the reset value might therefore vary between devices.
Page 314 Reference Manual CMU - Clock Management Unit Name Reset Access Description ENCHOP Enable Comparator Chopping Set to enable comparator chopping. This improves average frequency accuracy at the cost of increased jitter. ENVREF Enable Duty Cycling of Vref Set to enable duty cycling of vref. Clear during calibration of LFRCO. Only change when LFRCO is off. 15:9 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 315: Cmu_Hfxoctrl - Hfxo Control Register
Reference Manual CMU - Clock Management Unit 11.5.5 CMU_HFXOCTRL - HFXO Control Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions AUTOSTARTRDY- Automatically Start HFXO on RAC Wake-up and Select It Upon...
Page 316 Reference Manual CMU - Clock Management Unit Name Reset Access Description 23:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions XTO2GND Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off Set to enable grounding of HFXTAL_P pin when HFXO oscillator is off XTI2GND Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off...
Page 317: Cmu_Hfxostartupctrl - Hfxo Startup Control
Reference Manual CMU - Clock Management Unit 11.5.6 CMU_HFXOSTARTUPCTRL - HFXO Startup Control Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:11...
Page 318: Cmu_Hfxosteadystatectrl - Hfxo Steady State Control
Reference Manual CMU - Clock Management Unit 11.5.7 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State Control Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:28 REGISHUPPER Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA Set to steady state value of REGISH + 3.
Page 319: Cmu_Hfxotimeoutctrl - Hfxo Timeout Control
Reference Manual CMU - Clock Management Unit 11.5.8 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:16...
Page 320 Reference Manual CMU - Clock Management Unit Name Reset Access Description 256CYCLES Timeout period of 256 cycles 1KCYCLES Timeout period of 1024 cycles 2KCYCLES Timeout period of 2048 cycles 4KCYCLES Timeout period of 4096 cycles 8KCYCLES Timeout period of 8192 cycles 16KCYCLES Timeout period of 16384 cycles 32KCYCLES...
Page 321 Reference Manual CMU - Clock Management Unit Name Reset Access Description 16KCYCLES Timeout period of 16384 cycles 32KCYCLES Timeout period of 32768 cycles silabs.com | Building a more connected world. Rev. 1.1 | 321...
Page 322: Cmu_Lfxoctrl - Lfxo Control Register
Reference Manual CMU - Clock Management Unit 11.5.9 CMU_LFXOCTRL - LFXO Control Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 26:24...
Page 323 Reference Manual CMU - Clock Management Unit Name Reset Access Description 12:11 GAIN LFXO Startup Gain The optimal value for maximum startup margin depends on the chosen XTAL. Refer to the device data sheet or Simplicity Studio for more information. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 324: Cmu_Calctrl - Calibration Control Register
Reference Manual CMU - Clock Management Unit 11.5.10 CMU_CALCTRL - Calibration Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 27:24...
Page 325 Reference Manual CMU - Clock Management Unit Name Reset Access Description PRSCH5 PRS Channel 5 selected as input PRSCH6 PRS Channel 6 selected as input PRSCH7 PRS Channel 7 selected as input PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10 PRS Channel 10 selected as input...
Page 326: Cmu_Calcnt - Calibration Counter Register
Reference Manual CMU - Clock Management Unit 11.5.11 CMU_CALCNT - Calibration Counter Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:0...
Page 327: Cmu_Oscencmd - Oscillator Enable/Disable Command Register
Reference Manual CMU - Clock Management Unit 11.5.12 CMU_OSCENCMD - Oscillator Enable/Disable Command Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFXODIS...
Page 328: Cmu_Cmd - Command Register
Reference Manual CMU - Clock Management Unit 11.5.13 CMU_CMD - Command Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions HFXOSHUNTOPT- HFXO Shunt Current Optimization Start...
Page 329: Cmu_Dbgclksel - Debug Trace Clock Select
Reference Manual CMU - Clock Management Unit 11.5.14 CMU_DBGCLKSEL - Debug Trace Clock Select Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Debug Trace Clock...
Page 330: Cmu_Lfaclksel - Low Frequency A Clock Select Register
Reference Manual CMU - Clock Management Unit 11.5.16 CMU_LFACLKSEL - Low Frequency A Clock Select Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Clock Select for LFA...
Page 331: Cmu_Lfeclksel - Low Frequency E Clock Select Register
Reference Manual CMU - Clock Management Unit 11.5.18 CMU_LFECLKSEL - Low Frequency E Clock Select Register Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Clock Select for LFE...
Page 332: Cmu_Status - Status Register
Reference Manual CMU - Clock Management Unit 11.5.19 CMU_STATUS - Status Register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ULFRCOPHASE ULFRCO Clock Phase...
Page 333 Reference Manual CMU - Clock Management Unit Name Reset Access Description CALRDY Calibration Ready Calibration is Ready (0 when calibration is ongoing). 15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFXORDY LFXO Ready...
Page 334: Cmu_Hfclkstatus - Hfclk Status Register
Reference Manual CMU - Clock Management Unit 11.5.20 CMU_HFCLKSTATUS - HFCLK Status Register Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SELECTED...
Page 335: Cmu_Hfxotrimstatus - Hfxo Trim Status
Reference Manual CMU - Clock Management Unit 11.5.21 CMU_HFXOTRIMSTATUS - HFXO Trim Status Offset Bit Position 0x09C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 10:7...
Page 336: Cmu_If - Interrupt Flag Register
Reference Manual CMU - Clock Management Unit 11.5.22 CMU_IF - Interrupt Flag Register Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description CMUERR CMU Error Interrupt Flag Set upon illegal CMU write attempt (e.g. writing CMU_LFRCOCTRL while LFRCOBSY is set). Reserved To ensure compatibility with future devices, always write bits to 0.
Page 337 Reference Manual CMU - Clock Management Unit Name Reset Access Description HFXODISERR HFXO Disable Error Interrupt Flag Set when software tries to disable/deselect the HFXO in case the automatic enable/select reason is met. The HFXO was not disabled/deselected. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CALOF...
Page 338: Cmu_Ifs - Interrupt Flag Set Register
Reference Manual CMU - Clock Management Unit 11.5.23 CMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description CMUERR Set CMUERR Interrupt Flag Write 1 to set the CMUERR interrupt flag Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ULFRCOEDGE...
Page 339 Reference Manual CMU - Clock Management Unit Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CALOF Set CALOF Interrupt Flag Write 1 to set the CALOF interrupt flag CALRDY Set CALRDY Interrupt Flag Write 1 to set the CALRDY interrupt flag...
Page 340: Cmu_Ifc - Interrupt Flag Clear Register
Reference Manual CMU - Clock Management Unit 11.5.24 CMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x0A8 Reset Access Name Name Reset Access Description CMUERR (R)W1 Clear CMUERR Interrupt Flag Write 1 to clear the CMUERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
Page 341 Reference Manual CMU - Clock Management Unit Name Reset Access Description HFXOPEAKDETERR 0 (R)W1 Clear HFXOPEAKDETERR Interrupt Flag Write 1 to clear the HFXOPEAKDETERR interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). HFXOAUTOSW (R)W1 Clear HFXOAUTOSW Interrupt Flag...
Page 342: Cmu_Ien - Interrupt Enable Register
Reference Manual CMU - Clock Management Unit 11.5.25 CMU_IEN - Interrupt Enable Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description CMUERR CMUERR Interrupt Enable Enable/disable the CMUERR interrupt Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ULFRCOEDGE...
Page 343 Reference Manual CMU - Clock Management Unit Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CALOF CALOF Interrupt Enable Enable/disable the CALOF interrupt CALRDY CALRDY Interrupt Enable Enable/disable the CALRDY interrupt AUXHFRCORDY AUXHFRCORDY Interrupt Enable...
Page 344: Cmu_Hfbusclken0 - High Frequency Bus Clock Enable Register
Reference Manual CMU - Clock Management Unit 11.5.26 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0 Offset Bit Position 0x0B0 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions GPCRC...
Page 345: Cmu_Hfperclken0 - High Frequency Peripheral Clock Enable Register 0
Reference Manual CMU - Clock Management Unit 11.5.27 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 Offset Bit Position 0x0C0 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TRNG0...
Page 346: Cmu_Hfradioaltclken0 - High Frequency Alternate Radio Peripheral Clock Enable Register 0
Reference Manual CMU - Clock Management Unit Name Reset Access Description TIMER0 Timer 0 Clock Enable Set to enable the clock for TIMER0. 11.5.28 CMU_HFRADIOALTCLKEN0 - High Frequency Alternate Radio Peripheral Clock Enable Register 0 Offset Bit Position 0x0CC Reset Access Name Name...
Page 347: Cmu_Lfbclken0 - Low Frequency B Clock Enable Register 0 (Async Reg)
Reference Manual CMU - Clock Management Unit 11.5.30 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) Offset Bit Position 0x0E8 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LEUART0...
Page 348: Cmu_Hfpresc - High Frequency Clock Prescaler Register
Reference Manual CMU - Clock Management Unit 11.5.32 CMU_HFPRESC - High Frequency Clock Prescaler Register Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 24:24...
Page 349: Cmu_Hfcorepresc - High Frequency Core Clock Prescaler Register
Reference Manual CMU - Clock Management Unit 11.5.33 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register Offset Bit Position 0x108 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 16:8...
Page 350: Cmu_Hfradiopresc - High Frequency Radio Peripheral Clock Prescaler Register
Reference Manual CMU - Clock Management Unit 11.5.35 CMU_HFRADIOPRESC - High Frequency Radio Peripheral Clock Prescaler Register Offset Bit Position 0x110 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 16:8...
Page 351: Cmu_Lfapresc0 - Low Frequency A Prescaler Register 0 (Async Reg)
Reference Manual CMU - Clock Management Unit 11.5.37 CMU_LFAPRESC0 - Low Frequency a Prescaler Register 0 (Async Reg) Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LESENSE...
Page 352: Cmu_Lfbpresc0 - Low Frequency B Prescaler Register 0 (Async Reg)
Reference Manual CMU - Clock Management Unit Name Reset Access Description DIV16384 LFACLK = LFACLK/16384 LETIMER0 DIV32768 LFACLK = LFACLK/32768 LETIMER0 11.5.38 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) Offset Bit Position 0x128 Reset Access Name Name Reset Access Description...
Page 353: Cmu_Lfepresc0 - Low Frequency E Prescaler Register 0 (Async Reg)
Reference Manual CMU - Clock Management Unit 11.5.39 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg) When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect Offset Bit Position 0x130 Reset Access Name Name...
Page 354: Cmu_Syncbusy - Synchronization Busy Register
Reference Manual CMU - Clock Management Unit 11.5.41 CMU_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFXOBSY...
Page 355 Reference Manual CMU - Clock Management Unit Name Reset Access Description CMU_LFRCOCTRL is busy synchronizing new value AUXHFRCOBSY AUXHFRCO Busy Used to check the synchronization status of CMU_AUXHFRCOCTRL. Value Description CMU_AUXHFRCOCTRL is ready for update CMU_AUXHFRCOCTRL is busy synchronizing new value HFRCOBSY HFRCO Busy Used to check the synchronization status of CMU_HFRCOCTRL.
Page 356 Reference Manual CMU - Clock Management Unit Name Reset Access Description LFBCLKEN0 Low Frequency B Clock Enable 0 Busy Used to check the synchronization status of CMU_LFBCLKEN0. Value Description CMU_LFBCLKEN0 is ready for update CMU_LFBCLKEN0 is busy synchronizing new value Reserved To ensure compatibility with future devices, always write bits to 0.
Page 357: Cmu_Freeze - Freeze Register
Reference Manual CMU - Clock Management Unit 11.5.42 CMU_FREEZE - Freeze Register Offset Bit Position 0x144 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REGFREEZE Register Update Freeze...
Page 358: Cmu_Pcntctrl - Pcnt Control Register
Reference Manual CMU - Clock Management Unit 11.5.43 CMU_PCNTCTRL - PCNT Control Register Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PCNT0CLKSEL...
Page 359: Cmu_Adcctrl - Adc Control Register
Reference Manual CMU - Clock Management Unit 11.5.44 CMU_ADCCTRL - ADC Control Register Offset Bit Position 0x15C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ADC0CLKINV...
Page 360: Cmu_Routepen - I/O Routing Pin Enable Register
Reference Manual CMU - Clock Management Unit 11.5.45 CMU_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x170 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLKIN0PEN...
Page 361: Cmu_Routeloc0 - I/O Routing Location Register
Reference Manual CMU - Clock Management Unit 11.5.46 CMU_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x174 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 362: Cmu_Routeloc1 - I/O Routing Location Register
Reference Manual CMU - Clock Management Unit 11.5.47 CMU_ROUTELOC1 - I/O Routing Location Register Offset Bit Position 0x178 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLKIN0LOC...
Page 363: Cmu_Lock - Configuration Lock Register
Reference Manual CMU - Clock Management Unit 11.5.48 CMU_LOCK - Configuration Lock Register Offset Bit Position 0x180 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
Page 364: Smu - Security Management Unit
Reference Manual SMU - Security Management Unit 12. SMU - Security Management Unit Quick Facts What? The Security Management Unit (SMU) forms the control and status/reporting component of bus-level security in the EFR32. Why? Enables a robust and low-energy security solution at the system level How? Hardware context switching and access control pro-...
Page 365: Functional Description
Reference Manual SMU - Security Management Unit 12.3 Functional Description An overview of the SMU module within the system is shown in Figure 12.1 Bus-Level Security System View on page 365. IRQs ARM Core Control/Status Memory Space Peripherals Bus Matrix SRAM Code Figure 12.1.
Page 366: Programming Model
Reference Manual SMU - Security Management Unit 12.3.2 Programming Model The SMU does not provide any access control out of reset and needs to be configured by software. SMU access controls should be configured along with the MPU configuration. This is typically performed in a bootloader or other low level RTOS kernel/supervisor code prior to user code or other non-privileged code execution.
Page 367: Register Map
Reference Manual SMU - Security Management Unit 12.3.2.2 PPU Control The PPU_CTRL register provides an ENABLE bit that allows bypassing all PPU checking when set to 0. In this case, the rest of the PPU registers have no effect, and no access faults will occur. This is the reset state of the SMU. When the ENABLE bit of PPU_CTRL register is asserted, access protection is configured on a peripheral-by-peripheral basis using the SMU_PPUPATDx register(s).
Page 368: Register Description
Reference Manual SMU - Security Management Unit 12.5 Register Description 12.5.1 SMU_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PPUPRIV...
Page 369: Smu_Ifc - Interrupt Flag Clear Register
Reference Manual SMU - Security Management Unit 12.5.3 SMU_IFC - Interrupt Flag Clear Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PPUPRIV...
Page 370: Smu_Ppuctrl - Ppu Control Register
Reference Manual SMU - Security Management Unit 12.5.5 SMU_PPUCTRL - PPU Control Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ENABLE...
Page 371: Smu_Ppupatd0 - Ppu Privilege Access Type Descriptor 0
Reference Manual SMU - Security Management Unit 12.5.6 SMU_PPUPATD0 - PPU Privilege Access Type Descriptor 0 Set peripheral bits to 1 to mark as privileged access only Offset Bit Position 0x050 Reset Access Name Name Reset Access Description Security Management Unit access control bit Access control only for SMU RTCC Real-Time Counter and Calendar access control bit...
Page 372 Reference Manual SMU - Security Management Unit Name Reset Access Description GPCRC General Purpose CRC access control bit Access control only for GPCRC Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FPUEH FPU Exception Handler access control bit...
Page 373: Smu_Ppupatd1 - Ppu Privilege Access Type Descriptor 1
Reference Manual SMU - Security Management Unit 12.5.7 SMU_PPUPATD1 - PPU Privilege Access Type Descriptor 1 Set peripheral bits to 1 to mark as privileged access only Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 374: Smu_Ppufs - Ppu Fault Status
Reference Manual SMU - Security Management Unit 12.5.8 SMU_PPUFS - PPU Fault Status Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIPHID...
Page 375 Reference Manual SMU - Security Management Unit Name Reset Access Description Security Management Unit TIMER0 Timer 0 TIMER1 Timer 1 TRNG0 True Random Number Generator 0 USART0 Universal Synchronous/Asynchronous Receiver/Transmitter 0 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter 1 WDOG0 Watchdog 0 WDOG1 Watchdog 1 WTIMER0 Wide Timer 0...
Page 376: Rtcc - Real Time Counter And Calendar
Reference Manual RTCC - Real Time Counter and Calendar 13. RTCC - Real Time Counter and Calendar Quick Facts What? The Real Time Counter and Calendar (RTCC) is a 32-bit counter ensuring timekeeping in low energy 2 3 4 modes. The RTCC also includes a calendar mode for easy time and date keeping.
Page 377: Functional Description
Reference Manual RTCC - Real Time Counter and Calendar 13.3 Functional Description The RTCC is a 32-bit up-counter with three Capture/Compare channels. In addition, the RTCC includes a 15-bit pre-counter which can be used as an independent counter or to prescale the main counter. An overview of the RTCC module is shown in Figure 13.1 RTCC Overview on page 377.
Page 378: Counter
Reference Manual RTCC - Real Time Counter and Calendar 13.3.1 Counter The RTCC consists of two counters; the 32-bit main counter, RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode), and a 15- bit pre-counter, RTCC_PRECNT. The pre-counter can be used as an independent counter or to generate a specific frequency for the main counter.
Page 379 Reference Manual RTCC - Real Time Counter and Calendar 13.3.1.1 Normal Mode The main counter can receive a tick based on different tappings from the pre-counter, allowing the ticks to be power of 2 divisions of the LFCLK . For more accurate configuration of the tick frequency, RTCC_CC0_CCV[14:0] can be used as a top value for RTCC RTCC_PRECNT.
Page 380 Reference Manual RTCC - Real Time Counter and Calendar 13.3.1.2 Calendar Mode The RTCC includes a calendar mode which implements time and date decoding in hardware. Calendar mode is enabled by configuring CNTMODE in RTCC_CTRL to CALENDAR. When in calendar mode, the counter value is available in RTCC_TIME and RTCC_DATE. RTCC_TIME shows seconds, minutes, and hours while RTCC_DATE shows day of month, month, year, and day of week.
Page 381 Reference Manual RTCC - Real Time Counter and Calendar 13.3.1.3 RTCC Initialization The counters of the RTCC, RTCC_CNT (RTCC_TIME and RTCC_DATE in calendar mode) and RTCC_PRECNT, can at any time be written by software, as long as the registers are not locked using RTCC_LOCKKEY. All RTCC registers use the immediate synchroniza- tion scheme, described in 4.3.1 Writing.
Page 382: Capture/Compare Channels
Reference Manual RTCC - Real Time Counter and Calendar 13.3.2 Capture/Compare Channels Three capture/compare channels are available in the RTCC. Each channel can be configured as input capture or output compare, by setting the corresponding MODE in the RTCC_CCx_CTRL register. RTCC_CNT RTCC_CC0_CCV RTCC_CC1_CCV...
Page 383 Reference Manual RTCC - Real Time Counter and Calendar RTCC_CCx_CTRL_COMPBASE = CNT PRECNT MASK Compare match MASK CCx_CCV RTCC_CCx_CTRL_COMPBASE = PRECNT 0 14 PRECNT MASK Compare match MASK CCx_CCV Figure 13.4. RTCC Compare base illustration Table 13.3 RTCC Capture/Compare Subjects on page 383 summarizes which registers being subject to comparison for different con- figurations of RTCC_CTRL_CNTMODE and RTCC_CCx_CTRL_COMPBASE.
Page 384: Interrupts And Prs Output
Reference Manual RTCC - Real Time Counter and Calendar RTCC_DATE RTCC_TIME [0b000, [DAYOMT, DAYOW] DAYOMU] RTCC_CCx_CTRL_DAYCC [MONTHT,MONTHU] MASK Compare match MASK [MONTHT,MONTHU] [DAYT,DAYU] RTCC_CCx_DATE RTCC_CCx_TIME Figure 13.5. RTCC Compare in calendar mode, COMPBASE = CNT To generate periodically recurring events, it is possible to mask out parts of the compare match values. By configuring COMPMASK in RTCC_CCx_CTRL, parts of the compare values will be masked out, limiting which part of the compare register being subject to com- parison with the counter.
Page 385: Energy Mode Availability
Reference Manual RTCC - Real Time Counter and Calendar 13.3.3.1 Main Counter Tick PRS Output To output the ticks for the main counter on PRS, it is possible to use a Capture/Compare channel and mask all the bits, i.e. RTCC_CCx_CTRL_COMPBASE=CNT and RTCC_CCx_CTRL_COMPMASK=31. PRS output of main counter ticks does not work if the main counter is not prescaled.
Page 386: Register Map
Reference Manual RTCC - Real Time Counter and Calendar 13.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RTCC_CTRL Control Register 0x004 RTCC_PRECNT Pre-Counter Value Register 0x008 RTCC_CNT Counter Value Register 0x00C RTCC_COMBCNT Combined Pre-Counter and Counter Value Register...
Page 387: Register Description
Reference Manual RTCC - Real Time Counter and Calendar 13.5 Register Description 13.5.1 RTCC_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset...
Page 388 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description DIV4 = LFECLK RTCC DIV8 = LFECLK RTCC DIV16 = LFECLK RTCC DIV32 = LFECLK RTCC DIV64 = LFECLK RTCC DIV128 = LFECLK /128 RTCC DIV256 = LFECLK /256 RTCC DIV512...
Page 389: Rtcc_Precnt - Pre-Counter Value Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description...
Page 390: Rtcc_Combcnt - Combined Pre-Counter And Counter Value Register
Reference Manual RTCC - Real Time Counter and Calendar 13.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:15 CNTLSB 0x00000 Counter Value Gives access to the 17 LSBs of the main counter, CNT. Register will be read as zero when RTCC_CTRL_CNTMODE = CALENDAR.
Page 391: Rtcc_Time - Time Of Day Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.5 RTCC_TIME - Time of Day Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x010 Reset Access Name Name Reset Access...
Page 392: Rtcc_Date - Date Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.6 RTCC_DATE - Date Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:27...
Page 393: Rtcc_If - Rtcc Interrupt Flags
Reference Manual RTCC - Real Time Counter and Calendar 13.5.7 RTCC_IF - RTCC Interrupt Flags Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MONTHTICK...
Page 394: Rtcc_Ifs - Interrupt Flag Set Register
Reference Manual RTCC - Real Time Counter and Calendar 13.5.8 RTCC_IFS - Interrupt Flag Set Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MONTHTICK...
Page 395: Rtcc_Ifc - Interrupt Flag Clear Register
Reference Manual RTCC - Real Time Counter and Calendar 13.5.9 RTCC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MONTHTICK...
Page 396: Rtcc_Ien - Interrupt Enable Register
Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description (R)W1 Clear OF Interrupt Flag Write 1 to clear the OF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
Page 397: Rtcc_Status - Status Register
Reference Manual RTCC - Real Time Counter and Calendar 13.5.11 RTCC_STATUS - Status Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:0 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13.5.12 RTCC_CMD - Command Register...
Page 398: Rtcc_Powerdown - Retention Ram Power-Down Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.14 RTCC_POWERDOWN - Retention RAM Power-down Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x034 Reset Access Name Name Reset Access...
Page 399: Rtcc_Em4Wuen - Wake Up Enable
Reference Manual RTCC - Real Time Counter and Calendar 13.5.16 RTCC_EM4WUEN - Wake Up Enable Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM4WU...
Page 400: Rtcc_Ccx_Ctrl - Cc Channel Control Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x040 Reset Access Name Name Reset Access...
Page 401 Reference Manual RTCC - Real Time Counter and Calendar Name Reset Access Description PRSCH6 PRS Channel 6 selected as input PRSCH7 PRS Channel 7 selected as input PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10 PRS Channel 10 selected as input PRSCH11...
Page 402: Rtcc_Ccx_Ccv - Capture/Compare Value Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x044 Reset Access Name Name Reset Access Description...
Page 403: Rtcc_Ccx_Time - Capture/Compare Time Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x048 Reset Access Name Name Reset Access Description...
Page 404: Rtcc_Ccx_Date - Capture/Compare Date Register (Async Reg)
Reference Manual RTCC - Real Time Counter and Calendar 13.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x04C Reset Access Name Name Reset Access Description...
Page 405: Wdog - Watchdog Timer
Reference Manual WDOG - Watchdog Timer 14. WDOG - Watchdog Timer Quick Facts What? The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can be enabled in all energy modes as long as the low frequency clock source is available.
Page 406: Clock Source
Reference Manual WDOG - Watchdog Timer 14.3.1 Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOGn_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOGn_CTRL can be written to prevent accidental disabling of the selected clocks.
Page 407: Window Interrupt
Reference Manual WDOG - Watchdog Timer 14.3.6 Window Interrupt This interrupt occurs when the watchdog is cleared below a certain threshold. This threshold is given by the formula: 3+PERSEL = (2 ) * (WINSEL/8) + 1)/f, WARNING where f is the frequency of the selected clock. This value will be approximately 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, or 87.5% of the timeout value based on the WINSEL field of the WDOGn_CTRL.
Page 408: Prs As Watchdog Clear
Reference Manual WDOG - Watchdog Timer 14.3.7 PRS as Watchdog Clear The first PRS channel (selected by register WDOGn_PCH0_PRSCTRL) can be used to clear the watchdog counter. To enable this fea- ture, CLRSRC must be set to 1. Figure 14.2 PRS Clearing WDOG on page 408 shows how the PRS channel takes over the WDOG clear function.
Page 409: Register Map
Reference Manual WDOG - Watchdog Timer 14.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 WDOG_CTRL Control Register 0x004 WDOG_CMD Command Register 0x008 WDOG_SYNCBUSY Synchronization Busy Register 0x00C WDOGn_PCH0_PRSCTRL PRS Control Register 0x010 WDOGn_PCH1_PRSCTRL PRS Control Register...
Page 410: Register Description
Reference Manual WDOG - Watchdog Timer 14.5 Register Description 14.5.1 WDOG_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset Access Description WDOGRSTDIS...
Page 411 Reference Manual WDOG - Watchdog Timer Name Reset Access Description 23:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16 WARNSEL Watchdog Timeout Period Select Select watchdog warning timeout period. Value Description Disabled.
Page 412 Reference Manual WDOG - Watchdog Timer Name Reset Access Description Timeout period of 256k watchdog clock cycles. Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SWOSCBLOCK Software Oscillator Disable Block Set to disallow disabling of the selected WDOG oscillator.
Page 413: Wdog_Cmd - Command Register (Async Reg)
Reference Manual WDOG - Watchdog Timer Name Reset Access Description Watchdog Timer Enable Set to enabled watchdog timer. 14.5.2 WDOG_CMD - Command Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004...
Page 414: Wdog_Syncbusy - Synchronization Busy Register
Reference Manual WDOG - Watchdog Timer 14.5.3 WDOG_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PCH1_PRSCTRL PCH1_PRSCTRL Register Busy...
Page 415: Wdogn_Pchx_Prsctrl - Prs Control Register (Async Reg)
Reference Manual WDOG - Watchdog Timer 14.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 416: Wdog_If - Watchdog Interrupt Flags
Reference Manual WDOG - Watchdog Timer 14.5.5 WDOG_IF - Watchdog Interrupt Flags Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1 PRS Channel One Event Missing Interrupt Flag...
Page 417: Wdog_Ifs - Interrupt Flag Set Register
Reference Manual WDOG - Watchdog Timer 14.5.6 WDOG_IFS - Interrupt Flag Set Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1...
Page 418: Wdog_Ifc - Interrupt Flag Clear Register
Reference Manual WDOG - Watchdog Timer 14.5.7 WDOG_IFC - Interrupt Flag Clear Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1...
Page 419: Wdog_Ien - Interrupt Enable Register
Reference Manual WDOG - Watchdog Timer 14.5.8 WDOG_IEN - Interrupt Enable Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PEM1 PEM1 Interrupt Enable...
Page 420: Prs - Peripheral Reflex System
Reference Manual PRS - Peripheral Reflex System 15. PRS - Peripheral Reflex System Quick Facts What? The PRS (Peripheral Reflex System) allows configu- rable, fast, and autonomous communication be- tween peripherals. Why? Events and signals from one peripheral can be used as input signals or triggered by other peripherals.
Page 421: Functional Description
Reference Manual PRS - Peripheral Reflex System 15.3 Functional Description An overview of the PRS module is shown in Figure 15.1 PRS Overview on page 421. The PRS contains 12 Reflex channels. All chan- nels can select any Reflex signal offered by the producers. The consumers can choose which PRS channel to listen to and perform actions based on the Reflex signals routed through that channel.
Page 422: Producers
Reference Manual PRS - Peripheral Reflex System 15.3.1.2 Edge Detection and Clock Domains Using EDSEL in PRS_CHx_CTRL, edge detection can be applied to a PRS signal. When edge detection is enabled, changes in the PRS input will result in a pulse on the PRS channel. This requires that the ASYNC bit in PRS_CHx_CTRL is cleared. Signals on the PRS input must be at least one HFCLK period wide in order to be detected properly.
Page 423: Consumers
Reference Manual PRS - Peripheral Reflex System 15.3.3 Consumers Consumer peripherals (Listed in Table 15.1 Reflex Consumers on page 423) can be set to listen to a PRS channel and perform an action based on the signal received on that channel. While most consumers can handle either only pulse input or only level input, some can handle both pulse and level inputs.
Page 424: Event On Prs
Reference Manual PRS - Peripheral Reflex System Module Reflex Input Input Format LESENSE Scan Start Pulse LESENSE Decoder Bit 0 Level LESENSE Decoder Bit 1 Level LESENSE Decoder Bit 2 Level LESENSE Decoder Bit 3 Level WDOG Peripheral Watchdog Pulse LETIMER Start LETIMER Pulse...
Page 425: Example
Reference Manual PRS - Peripheral Reflex System 15.3.6 Example The example below (illustrated in Figure 15.3 TIMER0 Overflow Starting ADC0 Single Conversions Through PRS Channel 5. on page 425) shows how to set up ADC0 to start single conversions every time TIMER0 overflows (one HFPERCLK cycle high pulse), using PRS channel 5: •...
Page 426: Register Description
Reference Manual PRS - Peripheral Reflex System 15.5 Register Description 15.5.1 PRS_SWPULSE - Software Pulse Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11PULSE...
Page 427: Prs_Swlevel - Software Level Register
Reference Manual PRS - Peripheral Reflex System 15.5.2 PRS_SWLEVEL - Software Level Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11LEVEL...
Page 428: Prs_Routepen - I/O Routing Pin Enable Register
Reference Manual PRS - Peripheral Reflex System 15.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11PEN...
Page 429: Prs_Routeloc0 - I/O Routing Location Register
Reference Manual PRS - Peripheral Reflex System 15.5.4 PRS_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
Page 430 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC3 Location 3 LOC4 Location 4 LOC5 Location 5 LOC6 Location 6 LOC7 Location 7 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 431 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description silabs.com | Building a more connected world. Rev. 1.1 | 431...
Page 432: Prs_Routeloc1 - I/O Routing Location Register
Reference Manual PRS - Peripheral Reflex System 15.5.5 PRS_ROUTELOC1 - I/O Routing Location Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
Page 433 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC7 Location 7 LOC8 Location 8 LOC9 Location 9 LOC10 Location 10 LOC11 Location 11 LOC12 Location 12 LOC13 Location 13 LOC14 Location 14 LOC15 Location 15 LOC16 Location 16 LOC17 Location 17 15:14...
Page 434: Prs_Routeloc2 - I/O Routing Location Register
Reference Manual PRS - Peripheral Reflex System 15.5.6 PRS_ROUTELOC2 - I/O Routing Location Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
Page 435 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 LOC4 Location 4 LOC5 Location 5 LOC6 Location 6 LOC7 Location 7 LOC8 Location 8 LOC9 Location 9 LOC10 Location 10 LOC11 Location 11 LOC12...
Page 436: Prs_Ctrl - Control Register
Reference Manual PRS - Peripheral Reflex System 15.5.7 PRS_CTRL - Control Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SEVONPRSSEL SEVONPRS PRS Channel Select...
Page 437: Prs_Dmareq0 - Dma Request 0 Register
Reference Manual PRS - Peripheral Reflex System 15.5.8 PRS_DMAREQ0 - DMA Request 0 Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRSSEL...
Page 438: Prs_Dmareq1 - Dma Request 1 Register
Reference Manual PRS - Peripheral Reflex System 15.5.9 PRS_DMAREQ1 - DMA Request 1 Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRSSEL...
Page 439: Prs_Peek - Prs Channel Values
Reference Manual PRS - Peripheral Reflex System 15.5.10 PRS_PEEK - PRS Channel Values Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH11VAL...
Page 440: Prs_Chx_Ctrl - Channel Control Register
Reference Manual PRS - Peripheral Reflex System 15.5.11 PRS_CHx_CTRL - Channel Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ASYNC Asynchronous Reflex...
Page 441 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 14:8 SOURCESEL 0x00 Source Select Select input source to PRS channel. Value Mode Description 0b0000000 NONE No source selected 0b0000001 PRSL Peripheral Reflex System 0b0000010 PRSH Peripheral Reflex System 0b0000011 ACMP0 Analog Comparator 0...
Page 442 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b001 PRSCH1 PRS channel 1 PRSCH1 (Asynchronous) 0b010 PRSCH2 PRS channel 2 PRSCH2 (Asynchronous) 0b011 PRSCH3 PRS channel 3 PRSCH3 (Asynchronous) 0b100 PRSCH4 PRS channel 4 PRSCH4 (Asynchronous) 0b101 PRSCH5 PRS channel 5 PRSCH5 (Asynchronous) 0b110...
Page 443 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b010 LESENSESCANRES10 LESENSE SCANRES register, bit 10 LESENSESCANRES10 (Asyn- chronous) 0b011 LESENSESCANRES11 LESENSE SCANRES register, bit 11 LESENSESCANRES11 (Asyn- chronous) 0b100 LESENSESCANRES12 LESENSE SCANRES register, bit 12 LESENSESCANRES12 (Asyn- chronous) 0b101 LESENSESCANRES13 LESENSE SCANRES register, bit 13 LESENSESCANRES13 (Asyn-...
Page 444 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b110 GPIOPIN14 GPIO pin 14 GPIOPIN14 (Asynchronous) 0b111 GPIOPIN15 GPIO pin 15 GPIOPIN15 (Asynchronous) SOURCESEL = 0b0001110 (LETIMER0) 0b000 LETIMER0CH0 LETIMER CH0 Out LETIMER0CH0 (Asynchronous) 0b001 LETIMER0CH1 LETIMER CH1 Out LETIMER0CH1 (Asynchronous) SOURCESEL = 0b0001111 (PCNT0)
Page 445 Reference Manual PRS - Peripheral Reflex System Name Reset Access Description 0b011 TIMER0CC1 Timer 0 Compare/Capture 1 TIMER0CC1 0b100 TIMER0CC2 Timer 0 Compare/Capture 2 TIMER0CC2 SOURCESEL = 0b0111101 (TIMER1) 0b000 TIMER1UF Timer 1 Underflow TIMER1UF 0b001 TIMER1OF Timer 1 Overflow TIMER1OF 0b010 TIMER1CC0 Timer 1 Compare/Capture 0 TIMER1CC0...
Page 446: Pcnt - Pulse Counter
Reference Manual PCNT - Pulse Counter 16. PCNT - Pulse Counter Quick Facts What? The Pulse Counter (PCNT) decodes incoming pul- ses. The module has a quadrature mode which may be used to decode the speed and direction of a me- chanical shaft.
Page 447: Functional Description
Reference Manual PCNT - Pulse Counter 16.3 Functional Description An overview of the PCNT module is shown in Figure 16.1 PCNT Overview on page 447. CMU (conceptual) LFACLK Clock Triggered compare PCNTnCLK switch and clear control TCCMODE != DISABLED PCNT S0PRS Input OVR_SINGLE Edge...
Page 448 Reference Manual PCNT - Pulse Counter 16.3.1.3 Quadrature Decoder Modes Two different types of quadrature decoding is supported in the pulse counter: the externally clocked (Asynchronous) quadrature decod- ing and the oversampling (Synchronous) quadrature decoding. The externally clocked mode supports 1X quadrature decoding whereas the oversampling mode supports 1X, 2X and 4X quadrature decoding.
Page 449 Reference Manual PCNT - Pulse Counter 16.3.1.4 Externally Clocked Quadrature Decoder Mode This mode is enabled by writing EXTCLKQUAD to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field. The external pin clock source is configured by setting PCNT0CLKSEL in the CMU_PCNTCTRL register (11.
Page 450 Reference Manual PCNT - Pulse Counter Table 16.1. PCNT QUAD Mode Counter Control Function Inputs Control/Status S1IN posedge S1IN negedge Count Enable CNTDIR status bit Note: PCNTn_S1IN is sampled on both edges of PCNTn_S0IN. silabs.com | Building a more connected world. Rev.
Page 451 Reference Manual PCNT - Pulse Counter 16.3.1.5 Oversampling Quadrature Decoder Mode There are three Oversampling Quadrature Decoder Modes supported: 1X , 2X and 4X. These modes are enabled by writing OVS- QUAD1X, OVSQUAD2X and OVSQUAD4X, respectively, to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field.
Page 452 Reference Manual PCNT - Pulse Counter Relationship between inputs and its state STATE S1IN S0IN ‘b00 ‘b00 ‘b00 ‘b10 ‘b10 ‘b10 ‘b01 ‘b01 ‘b01 ‘b11 ‘b11 ‘b11 OVSQUAD2X mode OVSQUAD4X mode OVSQUAD1X mode Transitions between States All state transitions updates the Transitions between States and between counter...
Page 453 Reference Manual PCNT - Pulse Counter Period > 125 us S0IN S1IN Figure 16.5. PCNT Oversampling Quadrature Decoder 2X Mode Period > 125 us S0IN S1IN Figure 16.6. PCNT Oversampling Quadrature Decoder 4X Mode The above modes, by default are prone to flutter effects in the inputs PCNTn_S0IN and PCNTn_S1IN. When this occurs, the counter changes directions rapidly causing DIRCNG interrupts and unnecessarily waking the core.
Page 454: Hysteresis
Reference Manual PCNT - Pulse Counter 16.3.2 Hysteresis By default the pulse counter wraps to 0 when passing the configured top value, and wraps to the top value when counting down from 0. On these events, a system will likely want to wake up to store and track the overflow count. This is fine if the pulse counter is tracking a monotonic value or a value that does not change directions frequently.
Page 455: Auxiliary Counter
Reference Manual PCNT - Pulse Counter 16.3.3 Auxiliary Counter To be able to keep explicit track of counting in one direction in addition to the regular counter which counts both up and down, the auxiliary counter can be used. The pulse counter can, for instance, be configured to keep track of the absolute rotation of the wheel, while at the same time the auxiliary counter can keep track of how much the wheel has reversed.
Page 456: Triggered Compare And Clear
Reference Manual PCNT - Pulse Counter 16.3.4 Triggered Compare and Clear The pulse counter features triggered compare and clear. When enabled, a configurable trigger will induce a comparison between the main counter, PCNTn_CNT, and the top value, PCNTn_TOP. After the comparison, the counter is cleared. The trigger for a compare and clear event is configured in the TCCMODE bit-field in PCNTn_CTRL.
Page 457: Register Access
Reference Manual PCNT - Pulse Counter 16.3.5 Register Access The counter-clock domain may be clocked externally. To update the counter-clock domain registers from software in this mode, 2-3 clock pulses on the external clock are needed to synchronize accesses to the externally clocked domain. Clock source switching is controlled from the registers in the CMU (11.
Page 458: Edge Polarity
Reference Manual PCNT - Pulse Counter 16.3.8 Edge Polarity The edge polarity can be set by configuring the EDGE bit in the PCNTn_CTRL register. When this bit is cleared, the pulse counter counts positive edges of PCNTn_S0IN input. When this bit is set, the pulse counter counts negative edges in OVSSINGLE mode. Also, when the EDGE bit is set in the OVSSINGLE and EXTCLKSINGLE modes, the PCNTn_S1IN input is inverted.
Page 459 Reference Manual PCNT - Pulse Counter 16.3.10.2 Direction Change Interrupt The PCNTn_PCNT module sets the DIRCNG interrupt flag (PCNTn_IF register) for EXTCLKQUAD and OVSQUAD1X-4X modes when the direction of the quadrature code changes. The behavior of this interrupt in the EXTCLKQUAD mode is illustrated by Figure 16.13 PCNT Direction Change Interrupt (DIRCNG) Generation on page 459.
Page 460: Cascading Pulse Counters
Reference Manual PCNT - Pulse Counter 16.3.11 Cascading Pulse Counters When two or more Pulse Counters are available, it is possible to cascade them. For example two 16-bit Pulse Counters can be casca- ded to form a 32-bit pulse counter. This can be done with the help of the CNT UF/OF PRS and CNT DIR PRS ouputs. The figure Figure 16.14 PCNT Cascading to two 16-bit PCNT to form a 32-bit PCNT on page 460 illustrates this structure.
Page 461: Register Map
Reference Manual PCNT - Pulse Counter 16.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PCNTn_CTRL Control Register 0x004 PCNTn_CMD Command Register 0x008 PCNTn_STATUS Status Register 0x00C PCNTn_CNT Counter Value Register 0x010 PCNTn_TOP Top Value Register...
Page 462: Register Description
Reference Manual PCNT - Pulse Counter 16.5 Register Description 16.5.1 PCNTn_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset Access Description TOPBHFSEL...
Page 463 Reference Manual PCNT - Pulse Counter Name Reset Access Description PRSGATEEN PRS Gate Enable When set, the clock input to the pulse counter will be gated when the selected PRS input is the inverse of TCCPRSPOL. 23:22 TCCCOMP Triggered Compare and Clear Compare Mode Selects the mode for comparison upon a compare and clear event.
Page 464 Reference Manual PCNT - Pulse Counter Name Reset Access Description CNTDIR Non-Quadrature Mode Counter Direction Control The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EX- TCLKQUAD mode as the direction is automatically detected. Value Mode Description...
Page 465 Reference Manual PCNT - Pulse Counter Name Reset Access Description CNTRSTEN Enable CNT Reset The counter, CNT, is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT clock edges after this bit is cleared. If an external clock is used, the reset should be performed by setting and clearing the bit without pending for SYNCBUSY bit.
Page 466: Pcntn_Cmd - Command Register (Async Reg)
Reference Manual PCNT - Pulse Counter 16.5.2 PCNTn_CMD - Command Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 467: Pcntn_Cnt - Counter Value Register
Reference Manual PCNT - Pulse Counter 16.5.4 PCNTn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 0x0000...
Page 468: Pcntn_Topb - Top Value Buffer Register (Async Reg)
Reference Manual PCNT - Pulse Counter 16.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved...
Page 469: Pcntn_Ifs - Interrupt Flag Set Register
Reference Manual PCNT - Pulse Counter 16.5.8 PCNTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OQSTERR...
Page 470: Pcntn_Ifc - Interrupt Flag Clear Register
Reference Manual PCNT - Pulse Counter 16.5.9 PCNTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OQSTERR...
Page 471: Pcntn_Ien - Interrupt Enable Register
Reference Manual PCNT - Pulse Counter 16.5.10 PCNTn_IEN - Interrupt Enable Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OQSTERR OQSTERR Interrupt Enable...
Page 472: Pcntn_Routeloc0 - I/O Routing Location Register
Reference Manual PCNT - Pulse Counter 16.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 473 Reference Manual PCNT - Pulse Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions S0INLOC...
Page 474: Pcntn_Freeze - Freeze Register
Reference Manual PCNT - Pulse Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 16.5.12 PCNTn_FREEZE - Freeze Register Offset Bit Position 0x040...
Page 475: Pcntn_Syncbusy - Synchronization Busy Register
Reference Manual PCNT - Pulse Counter 16.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OVSCFG OVSCFG Register Busy...
Page 476: Pcntn_Input - Pcnt Input Register
Reference Manual PCNT - Pulse Counter 16.5.15 PCNTn_INPUT - PCNT Input Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions S1PRSEN S1IN PRS Enable...
Page 477: Pcntn_Ovscfg - Oversampling Config Register (Async Reg)
Reference Manual PCNT - Pulse Counter Name Reset Access Description PRSCH0 PRS Channel 0 selected. PRSCH1 PRS Channel 1 selected. PRSCH2 PRS Channel 2 selected. PRSCH3 PRS Channel 3 selected. PRSCH4 PRS Channel 4 selected. PRSCH5 PRS Channel 5 selected. PRSCH6 PRS Channel 6 selected.
Page 478: I2C - Inter-Integrated Circuit Interface
Reference Manual I2C - Inter-Integrated Circuit Interface 17. I2C - Inter-Integrated Circuit Interface Quick Facts What? The I C interface allows communication on I buses with the lowest energy consumption possible. Why? C is a popular serial bus that enables communica- tion with a number of external devices using only Gecko Device C master/slave...
Page 479: Functional Description
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3 Functional Description An overview of the I2C module is shown in Figure 17.1 I2C Overview on page 479. Peripheral Bus C Control and Transmit Buffer Receive Buffer Status (2-level FIFO) (2-level FIFO) I2Cn_SDA Symbol Transmit...
Page 480: I2C-Bus Overview
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1 I2C-Bus Overview The I C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in Figure 17.2 I2C-Bus Example on page 480. As a true multi-master bus it includes collision detection and arbitration to resolve situations where multiple masters transmit data at the same time without data loss.
Page 481 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus. All transactions on the bus begin with a START condition (S) and end with a STOP condition (P). As shown in Figure 17.4 I2C START and STOP Conditions on page 481, a START condition is generated by pulling the SDA line low while SCL is high, and a STOP condition is generated by pulling the SDA line high...
Page 482 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.2 Bus Transfer When a master wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The master then transmits the address of the slave it wishes to interact with and a single R/W bit telling whether it wishes to read from the slave (R/W bit set to 1) or write to the slave (R/W bit set to 0).
Page 483 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.3 Addresses C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains the address of the slave that the master wants to contact. In the 7-bit address space, several addresses are reserved. These addresses are summarized in Table 17.1 I2C Reserved I C Addresses on page...
Page 484: Enable And Reset
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.1.5 Arbitration, Clock Synchronization, Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration occurs when two devices try to drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain bus configuration.
Page 485: Arbitration
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.5 Arbitration Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value on SDA is sensed every time the I C module attempts to change its value. If the sensed value is different than the value the I C module tried to output, it is interpreted as a simultaneous transmission by another device, and that the I C module has lost arbitration.
Page 486 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.6.2 Receive Buffer and Shift Register The I C receiver uses a 2-level FIFO receive buffer and a receive shift register as shown in Figure 17.14 I2C Receive Buffer Operation on page 486. When a byte has been fully received by the receive shift register, it is loaded into the receive buffer if there is room for it, making the shift register empty to receive another byte.
Page 487: Master Operation
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7 Master Operation A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2Cn_CMD. The command schedules a START condition, and makes the I C module generate a start condition whenever the bus becomes free.
Page 488 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.1 Master State Machine The master state machine is shown in Figure 17.15 I2C Master State Machine on page 488. A master operation starts in the far left of the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when arriving at the right side of the state machine.
Page 489 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I C module.
Page 490 Reference Manual I2C - Inter-Integrated Circuit Interface When several interactions are possible from a set of pending commands, the interaction with the highest priority, i.e., the interaction closest to the top of Table 17.2 I2C Interactions in Prioritized Order on page 489 is applied to the bus.
Page 491 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.5 Master Transmitter To transmit data to a slave, the master must operate as a master transmitter. Table 17.3 I2C Master Transmitter on page 491 shows the states the I C module goes through while acting as a master transmitter. Every state where an interaction is required has the possi- ble interactions listed, along with the result of the interactions.
Page 492 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0x97 ADDR+W transmitted, ACK interrupt flag TXDATA DATA will be sent ACK received (BUSHOLD interrupt STOP STOP will be sent. Bus will be released flag) START Repeated start condition will be sent STOP + STOP will be sent and the bus released.
Page 493 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.7.6 Master Receiver To receive data from a slave, the master must operate as a master receiver, see Table 17.4 I2C Master Receiver on page 493. This is done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a master transmitter. The ad- dress byte loaded into the data register thus has to contain the 7-bit slave address in the 7 most significant bits of the byte, and have the least significant bit set.
Page 494 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0xB3 Data received RXDATA interrupt ACK + RXDA- ACK will be transmitted, reception continues flag(BUSHOLD inter- rupt flag) NACK + NACK will be transmitted, reception continues CONT + RXDATA ACK/NACK +...
Page 495: Bus States
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.8 Bus States The I2Cn_STATE register can be used to determine which state the I C module and the I C bus are in at a given time. The register consists of the STATE bit-field, which shows which state the I C module is at in any ongoing transmission, and a set of single-bits, which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I C module waiting for a soft-...
Page 496 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.9.1 Slave State Machine The slave state machine is shown in Figure 17.16 I2C Slave State Machine on page 496. The dotted lines show where I C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission pro- ceed.
Page 497 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.9.3 Slave Transmitter When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit. If there is no room in the receive shift register for the address, the bus will be held by the slave until room is available in the shift register.
Page 498 Reference Manual I2C - Inter-Integrated Circuit Interface I2Cn_STATE Description I2Cn_IF Required in- Response teraction 0xDD Data transmitted, NACK NACK interrupt flag None The slave goes idle received (BUSHOLD interrupt CONT + DATA will be transmitted flag) TXDATA Stop received SSTOP interrupt flag None The slave goes idle START...
Page 499: Transfer Automation
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.9.4 Slave Receiver A slave receiver operation is started in the same way as a slave transmitter operation, with the exception that the address transmitted by the master has the R/W bit cleared (W), indicating that the master wishes to write to the slave. The slave then goes into slave receiv- er mode.
Page 500: Using 10-Bit Addresses
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.10.1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, soft- ware is thus relieved of moving data to and from memory after each transferred byte. 17.3.10.2 Automatic ACK When AUTOACK in I2Cn_CTRL is set, an ACK is sent automatically whenever an ACK interaction is possible and no higher priority interactions are pending.
Page 501 Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.12.3 I2C-Bus Errors An I C-bus error occurs when a START or STOP condition is misplaced, which happens when the value on SDA changes while SCL is high during bit-transmission on the I C-bus.
Page 502: Dma Support
Reference Manual I2C - Inter-Integrated Circuit Interface 17.3.12.7 Clock Low Error The I C module can continue transmission in parallel with another device for the entire transaction, as long as the two communications are identical. A case may arise when (before an arbitration has been decided upon) the I C module decides to send out a repeated START or a STOP condition while the other device is still sending data.
Page 503: Register Map
Reference Manual I2C - Inter-Integrated Circuit Interface 17.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2Cn_CTRL Control Register 0x004 I2Cn_CMD Command Register 0x008 I2Cn_STATE State Register 0x00C I2Cn_STATUS Status Register 0x010 I2Cn_CLKDIV Clock Division Register...
Page 504: Register Description
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5 Register Description 17.5.1 I2Cn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 18:16...
Page 505 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description 13:12 BITO Bus Idle Timeout Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition. When in a bus transaction, i.e. the BUSY flag is set, a timer is started whenever SCL goes high. When the timer reaches the value defined by BITO, it sets the BITO interrupt flag.
Page 506 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description When a general call address is received, a software response is re- quired. ARBDIS Arbitration Disable A master or slave will not release the bus upon losing arbitration. Value Description When a device loses arbitration, the ARB interrupt flag is set and the bus is released.
Page 507: I2Cn_Cmd - Command Register
Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Value Description The I C module is disabled. And its internal state is cleared The I C module is enabled. 17.5.2 I2Cn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name...
Page 508: I2Cn_State - State Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.3 I2Cn_STATE - State Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions STATE Transmission State...
Page 509: I2Cn_Status - Status Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.4 I2Cn_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXFULL RX FIFO Full...
Page 510: I2Cn_Clkdiv - Clock Division Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.5 I2Cn_CLKDIV - Clock Division Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 0x000...
Page 511: I2Cn_Saddrmask - Slave Address Mask Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.7 I2Cn_SADDRMASK - Slave Address Mask Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions MASK...
Page 512: I2Cn_Rxdouble - Receive Buffer Double Data Register (Actionable Reads)
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads) Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
Page 513: I2Cn_Rxdoublep - Receive Buffer Double Data Peek Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
Page 514: I2Cn_Txdouble - Transmit Buffer Double Data Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
Page 515: I2Cn_If - Interrupt Flag Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.14 I2Cn_IF - Interrupt Flag Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
Page 516 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description RXDATAV Receive Data Valid Interrupt Flag Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read. TXBL Transmit Buffer Level Interrupt Flag Set when the transmit buffer becomes empty.
Page 517: I2Cn_Ifs - Interrupt Flag Set Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.15 I2Cn_IFS - Interrupt Flag Set Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
Page 518 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set TXC Interrupt Flag Write 1 to set the TXC interrupt flag ADDR Set ADDR Interrupt Flag Write 1 to set the ADDR interrupt flag RSTART Set RSTART Interrupt Flag Write 1 to set the RSTART interrupt flag START Set START Interrupt Flag...
Page 519: I2Cn_Ifc - Interrupt Flag Clear Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.16 I2Cn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
Page 520 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description MSTOP (R)W1 Clear MSTOP Interrupt Flag Write 1 to clear the MSTOP interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). NACK (R)W1 Clear NACK Interrupt Flag...
Page 521: I2Cn_Ien - Interrupt Enable Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.17 I2Cn_IEN - Interrupt Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:19 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLERR...
Page 522: I2Cn_Routepen - I/O Routing Pin Enable Register
Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description RXDATAV RXDATAV Interrupt Enable Enable/disable the RXDATAV interrupt TXBL TXBL Interrupt Enable Enable/disable the TXBL interrupt TXC Interrupt Enable Enable/disable the TXC interrupt ADDR ADDR Interrupt Enable Enable/disable the ADDR interrupt RSTART RSTART Interrupt Enable Enable/disable the RSTART interrupt...
Page 523: I2Cn_Routeloc0 - I/O Routing Location Register
Reference Manual I2C - Inter-Integrated Circuit Interface 17.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 524 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SDALOC...
Page 525 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 526: Usart - Universal Synchronous Asynchronous Receiver/Transmitter
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18. USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? The USART handles high-speed UART, SPI-bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embed- ded systems and the USART allows efficient com- munication with a wide range of external devices.
Page 527: Features
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.2 Features • Asynchronous and synchronous (SPI) communication • Full duplex and half duplex • Separate TX/RX enable • Separate receive / transmit multiple entry buffers, with additional separate shift registers • Programmable baud rate, generated as an fractional division from the peripheral clock (HFPERCLK USARTn •...
Page 528: Functional Description
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3 Functional Description An overview of the USART module is shown in Figure 18.1 USART Overview on page 528. This section describes all possible USART features. Refer to the device data sheet to see what features a specific USART instance supports.
Page 529: Modes Of Operation
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.1 Modes of Operation The USART operates in either asynchronous or synchronous mode. In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the bus master, and both the master and slave sample and transmit data according to this clock.
Page 530 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.
Page 531 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL. When MSBF is cleared, data in a frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first. The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL.
Page 532 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.3 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Figure 18.3 USART Baud Rate on page 532.
Page 533 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USARTn_OVS =00 USARTn_OVS =01 Desired baud USARTn_CLKDIV/256 Actual baud rate USARTn_CLKDIV/256 Actual baud rate rate [baud/s] Error % Error % (to 32nd position) [baud/s] (to 32nd position) [baud/s] 38400 38461.54 0.160 12.03125 38369.3 -0.080 57600...
Page 534 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.6 Transmit Buffer Operation The transmit-buffer is a multiple entry FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buf- fer, while using USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer.
Page 535 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.7 Frame Transmission Control The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of the written frame. The following options are available: • Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g.
Page 536 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.9 Receive Buffer Operation When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set.
Page 537 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.10 Blocking Incoming Data When using hardware frame recognition, as detailed in 18.3.2.20 Multi-Processor Mode 18.3.2.21 Collision Detection, it is necessa- ry to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer. This is accomplished by blocking incoming data.
Page 538 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.11 Clock Recovery and Filtering The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors. When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame.
Page 539 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/1 Figure 18.8. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices.
Page 540 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.14 Local Loopback The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default. This is not the only option howev- er. When LOOPBK in USARTn_CTRL is set, the receiver is connected to the U(S)n_TX pin as shown in Figure 18.9 USART Local Loopback on page 540.
Page 541 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.17 Single Data-link With External Driver Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of tristating the transmitter when receiving data, the external driver must be disabled. This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART.
Page 542 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.19 Large Frames As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when working with USART-frames of 10 or more data bits. To transmit such a frame, at least two elements must be available in the transmit buffer.
Page 543 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two buffer elements. If BYTESWAP is cleared, the least significant 8 bits of the received frame are loaded into the first element of the receive buffer, and the remaining bits are loaded into the second element, as shown in Figure 18.13 USART Reception of Large Frames on page...
Page 544 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.21 Collision Detection The USART supports a basic form of collision detection. When the receiver is connected to the output of the transmitter, either by using the LOOPBK bit in USARTn_CTRL or through an external connection, this feature can be used to detect whether data transmitted on the bus by the USART did get corrupted by a simultaneous transmission by another device on the bus.
Page 545 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.2.22 SmartCard Mode In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stop-bits (guard time), the 7816 data frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard time to indicate a parity error.
Page 546: Synchronous Operation
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 1/2 stop bit NAK or stop Stop 13 14 15 16 1 9 10 11 14 15 16 17 18 X Figure 18.17. USART SmartCard Stop Bit Sampling For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one of the timers.
Page 547 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.2 Clock Generation The bit-rate in synchronous mode is given by Figure 18.18 USART Synchronous Mode Bit Rate on page 547. As in the case of asyn- chronous operation, the clock division factor have a 15-bit integral part and a 5-bit fractional part. br = f /(2 x (1 + USARTn_CLKDIV/256)) HFPERCLK...
Page 548 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter RXDATAV flag is updated on the last sample clock edge of a transfer, while the RX overflow interrupt flag, RXOF, is set on the first sample clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL and TXC are updated on the first setup clock edge of the succeeding frame, or when CS is deasserted.
Page 549 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.7 Synchronous Half Duplex Communication Half duplex communication in synchronous mode is very similar to half duplex communication in asynchronous mode as detailed in 18.3.2.15 Asynchronous Half Duplex Communication. The main difference is that in this mode, the master must generate the bus clock even when it is not transmitting data, i.e.
Page 550 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.10 Major Modes The USART supports a set of different I2S formats as shown in Table 18.9 USART I2S Modes on page 550, but it is not limited to these modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO enables mono mode, i.e.
Page 551 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USn_CLK USn_CS (word select) USn_TX/ USn_RX Left channel Right channel Left channel Figure 18.23. USART Left-Justified I2S Waveform A right-justified stream is shown in Figure 18.24 USART Right-Justified I2S Waveform on page 551.
Page 552: Hardware Flow Control
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.3.11 Using I2S Mode When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits. 8 databits can be used in all modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared.
Page 553: Prs Clk Input
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.8 PRS CLK Input The USART can be configured to receive clock directly from a PRS channel by setting CLKPRS in USARTn_INPUT. The PRS channel used is selected using CLKPRSSEL in USARTn_INPUT. This is useful in synchronous slave mode and can together with RX PRS input be used to input data from PRS.
Page 554: Timer
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10 Timer In addition to the TX sequence timer, there is a versatile 8 bit timer that can generate up to three event pulses. These pulses can be used to create timing for a variety of uses such as RX timeout, break detection, response timeout, and RX enable delay. Transmission delay, CS setup, inter-character spacing, and CS hold use the TX sequence counter.
Page 555 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter TIMECMP2 TIMECMP1 TIMECMP0 TCMPn TXST RXACT TCMPVALn RXACTN TSTOP GP_CNT[7:0] clear DISABLE TCMP TXEOF Compare TCMPn enable RXACT RXEOF TSTART START_An RESTARTEN START_Bn START_A2 START_B2 START_A1 start START_B1 event START_A0 8 bit bit time GP_CNT[7:0] START_B0...
Page 556 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Application TSTARTn TSTOPn TCMPVALn Other Break Detect TSTART1 = RXACT TSTOP1 = TCMPVAL1 TCMP1 in USARTn_IEN RXACTN = 0x0C TX delayed start of transmission and TSTART0 = DISA- TSTOP0 = TCMP0, TCMPVAL0 TXDELAY = TCMP0, CSSETUP = CS setup BLE, TSTART1 =...
Page 557 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10.2 RX Timeout A receiver timeout function can be implemented by using the RX end of frame to start comparator 1 and look for the RX start bit RXACT to disable the comparator. See Table 18.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 555 for details on setting up this example.
Page 558 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10.4 TX Start Delay Some applications may require a delay before the start of transmission. This example in Figure 18.30 USART TXSEQ Timing on page shows the TXSEQ timer used to delay the start of transmission by 4 baud times before the start of CS, and by 2 baud times with CS asserted.
Page 559: Interrupts
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.10.8 Combined TX and RX Example This example describes how to alternate between TX and RX frames. This has a 28 baud-time space after RX and a 16 baud-time space after TX. The TSTART1 in USARTn_TIMECMP1 is set to RXEOF which uses the the receiver end of frame to start the timer. The TSTOP1 is set to TCMP1 to generate an event after 28 baud times.
Page 560: Irda Modulator/ Demodulator
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.3.12 IrDA Modulator/ Demodulator The IrDA modulator implements the physical layer of the IrDA specification, which is necessary for communication over IrDA. The mod- ulator takes the signal output from the USART module, and modulates it before it leaves the USART. In the same way, the input signal is demodulated before it enters the actual USART module.
Page 561: Register Map
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USARTn_CTRL Control Register 0x004 USARTn_FRAME USART Frame Format Register 0x008 USARTn_TRIGCTRL USART Trigger Control Register 0x00C USARTn_CMD Command Register...
Page 562: Register Description
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5 Register Description 18.5.1 USARTn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description SMSDELAY Synchronous Master Sample Delay Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher speeds MVDIS Majority Vote Disable...
Page 563 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Framing and parity errors disable the receiver ERRSDMA Halt DMA on Error When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only). Value Description Framing and parity errors have no effect on DMA requests from the USART...
Page 564 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Output from the transmitter is inverted before it is passed to U(S)n_TX RXINV Receiver Input Invert Setting this bit will invert the input to the USART receiver. Value Description Input is passed directly to the receiver Input is inverted before it is passed to the receiver...
Page 565 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description IDLEHIGH The bus clock used in synchronous mode has a high base value Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Oversampling...
Page 566 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description The USART operates in synchronous mode silabs.com | Building a more connected world. Rev. 1.1 | 566...
Page 567: Usartn_Frame - Usart Frame Format Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.2 USARTn_FRAME - USART Frame Format Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:12...
Page 568 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Each frame contains 6 data bits SEVEN Each frame contains 7 data bits EIGHT Each frame contains 8 data bits NINE Each frame contains 9 data bits Each frame contains 10 data bits ELEVEN Each frame contains 11 data bits TWELVE...
Page 569: Usartn_Trigctrl - Usart Trigger Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.3 USARTn_TRIGCTRL - USART Trigger Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:16...
Page 570 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TXARX2EN Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL When set, an RX end of frame will trigger the transmitter after TCMP2VAL bit times to force a minimum response delay TXARX1EN Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL When set, an RX end of frame will trigger the transmitter after TCMP1VAL bit times to force a minimum response delay...
Page 571: Usartn_Cmd - Command Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.4 USARTn_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLEARRX...
Page 572: Usartn_Status - Usart Status Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.5 USARTn_STATUS - USART Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 17:16...
Page 573: Usartn_Clkdiv - Clock Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TX Complete Set when a transmission has completed and no more data is available in the transmit buffer and shift register. Cleared when data is written to the transmit buffer. TXTRI Transmitter Tristated Set when the transmitter is tristated, and cleared when transmitter output is enabled.
Page 574: Usartn_Rxdatax - Rx Buffer Data Extended Register (Actionable Reads)
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FERR...
Page 575: Usartn_Rxdoublex - Rx Buffer Double Data Extended Register (Actionable Reads)
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) Offset Bit Position 0x020 Reset Access Name Name Reset Access Description FERR1 Data Framing Error 1 Set if data in buffer has a framing error. Can be the result of a break condition. PERR1 Data Parity Error 1 Set if data in buffer has a parity error (asynchronous mode only).
Page 576: Usartn_Rxdouble - Rx Fifo Double Data Register (Actionable Reads)
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
Page 577: Usartn_Rxdoublexp - Rx Buffer Double Data Extended Peek Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description FERRP1 Data Framing Error 1 Peek Set if data in buffer has a framing error. Can be the result of a break condition. PERRP1 Data Parity Error 1 Peek Set if data in buffer has a parity error (asynchronous mode only).
Page 578: Usartn_Txdatax - Tx Buffer Data Extended Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXENAT...
Page 579: Usartn_Txdata - Tx Buffer Data Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.14 USARTn_TXDATA - TX Buffer Data Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TXDATA...
Page 580: Usartn_Txdoublex - Tx Buffer Double Data Extended Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description RXENAT1 Enable RX After Transmission Set to enable reception after transmission. TXDISAT1 Clear TXEN After Transmission Set to disable transmitter and release data bus directly after transmission.
Page 581: Usartn_Txdouble - Tx Buffer Double Data Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:8...
Page 582: Usartn_If - Interrupt Flag Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.17 USARTn_IF - Interrupt Flag Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
Page 583 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RX Buffer Full Interrupt Flag Set when the receive buffer becomes full. RXDATAV RX Data Valid Interrupt Flag Set when data becomes available in the receive buffer. TXBL TX Buffer Level Interrupt Flag Set when buffer becomes empty if buffer level is set to 0x0, or when the number of empty TX buffer elements equals speci-...
Page 584: Usartn_Ifs - Interrupt Flag Set Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.18 USARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
Page 585 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Set TXC Interrupt Flag Write 1 to set the TXC interrupt flag silabs.com | Building a more connected world.
Page 586: Usartn_Ifc - Interrupt Flag Clear Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.19 USARTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
Page 587 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TXOF (R)W1 Clear TXOF Interrupt Flag Write 1 to clear the TXOF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). RXUF (R)W1 Clear RXUF Interrupt Flag...
Page 588: Usartn_Ien - Interrupt Enable Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.20 USARTn_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMP2...
Page 589 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RXFULL Interrupt Enable Enable/disable the RXFULL interrupt RXDATAV RXDATAV Interrupt Enable Enable/disable the RXDATAV interrupt TXBL TXBL Interrupt Enable Enable/disable the TXBL interrupt TXC Interrupt Enable Enable/disable the TXC interrupt silabs.com | Building a more connected world.
Page 590: Usartn_Irctrl - Irda Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.21 USARTn_IRCTRL - IrDA Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 11:8...
Page 591 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description IRPW IrDA TX Pulse Width Configure the pulse width generated by the IrDA modulator as a fraction of the configured USART bit period. Value Mode Description IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1...
Page 592: Usartn_Input - Usart Input Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.22 USARTn_INPUT - USART Input Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLKPRS...
Page 593 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description PRSCH0 PRS Channel 0 selected PRSCH1 PRS Channel 1 selected PRSCH2 PRS Channel 2 selected PRSCH3 PRS Channel 3 selected PRSCH4 PRS Channel 4 selected PRSCH5 PRS Channel 5 selected PRSCH6 PRS Channel 6 selected PRSCH7...
Page 594: Usartn_I2Sctrl - I2S Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.23 USARTn_I2SCTRL - I2S Control Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 10:8...
Page 595 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Enable I2S Mode Set the U(S)ART in I2S mode. silabs.com | Building a more connected world. Rev. 1.1 | 595...
Page 596: Usartn_Timing - Timing Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.24 USARTn_TIMING - Timing Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 CSHOLD...
Page 597 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 22:20...
Page 598: Usartn_Ctrlx - Control Register Extended
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.25 USARTn_CTRLX - Control Register Extended Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RTSINV...
Page 599: Usartn_Timecmp0 - Used To Generate Interrupts And Various Delays
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.26 USARTn_TIMECMP0 - Used to Generate Interrupts and Various Delays Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN...
Page 600 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMPVAL 0x00 Timer Comparator 0 When the timer equals TCMPVAL, this signals a TCMP0 event and sets the TCMP0 flag. This event can also be used to enable various USART functionality.
Page 601: Usartn_Timecmp1 - Used To Generate Interrupts And Various Delays
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.27 USARTn_TIMECMP1 - Used to Generate Interrupts and Various Delays Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN...
Page 602 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMPVAL 0x00 Timer Comparator 1 When the timer equals TCMPVAL, this signals a TCMP1 event and sets the TCMP1 flag. This event can also be used to enable various USART functionality.
Page 603: Usartn_Timecmp2 - Used To Generate Interrupts And Various Delays
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.28 USARTn_TIMECMP2 - Used to Generate Interrupts and Various Delays Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RESTARTEN...
Page 604 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 15:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TCMPVAL 0x00 Timer Comparator 2 When the timer equals TCMPVAL, this signals a TCMP2 event and sets the TCMP2 flag. This event can also be used to enable various USART functionality.
Page 605: Usartn_Routepen - I/O Routing Pin Enable Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RTSPEN...
Page 606 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXPEN RX Pin Enable When set, the RX/MISO pin of the USART is enabled. Value Description The U(S)n_RX (MISO) pin is disabled The U(S)n_RX (MISO) pin is enabled silabs.com | Building a more connected world.
Page 607: Usartn_Routeloc0 - I/O Routing Location Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x078 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24...
Page 608 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16...
Page 609 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 610 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXLOC...
Page 611 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 612: Usartn_Routeloc1 - I/O Routing Location Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 18.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 613 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 614 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 615: Leuart - Low Energy Universal Asynchronous Receiver/Transmitter
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Quick Facts What? The LEUART provides full UART communication us- ing a low frequency 32.768 kHz clock, and has spe- cial features for communication without CPU inter- vention.
Page 616: Features
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.2 Features • Low energy asynchronous serial communications • Full/half duplex communication • Separate TX / RX enable • Separate double buffered transmit buffer and receive buffer • Programmable baud rate, generated as a fractional division of the LFBCLK •...
Page 617: Functional Description
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3 Functional Description An overview of the LEUART module is shown in Figure 19.1 LEUART Overview on page 617. Peripheral Bus UART Control TX Buffer RX Buffer and status !RXBLOCK Start frame (STARTFRAME) Start frame interrupt Signal frame interrupt...
Page 618: Frame Format
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.1 Frame Format The frame format used by the LEUART consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.
Page 619: Clock Generation
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.3 Clock Generation The LEUART clock defines the transmission and reception data rate. The clock generator employs a fractional clock divider to allow baud rates that are not attainable by integral division of the 32.768 kHz clock that drives the LEUART. The clock divider used in the LEUART is a 14-bit value, with a 9-bit integral part and a 5-bit fractional part.
Page 620 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.4.1 Transmit Buffer Operation A frame can be loaded into the transmit buffer by writing to LEUARTn_TXDATA or LEUARTn_TXDATAX. Using LEUARTn_TXDATA allows 8 bits to be written to the buffer. If 9 bit frames are used, the 9th bit will in that case be set to the value of BIT8DV in LEUARTn_CTRL.
Page 621: Data Reception
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.5 Data Reception Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively samples the input looking for a transition from high to low indicating the start bit of a new frame. When a start bit is found, reception of the new frame begins if the receive shift register is empty and ready for new data.
Page 622 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.5.2 Blocking Incoming Data When using hardware frame recognition, as detailed in 19.3.5.6 Programmable Start Frame, 19.3.5.7 Programmable Signal Frame, and 19.3.5.8 Multi-Processor Mode, it is necessary to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer.
Page 623 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.5.5 Framing Error and Break Detection A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This can be the result of noise and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
Page 624: Loopback
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.5.8 Multi-Processor Mode To simplify communication between multiple processors and maintain compatibility with the USART, the LEUART supports a multi-pro- cessor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address.
Page 625: Transmission Delay
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.7.1 Single Data-link In this setup, the LEUART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in LEUARTn_CTRL, which connects the receiver to the transmitter output. Because they are both connected to the same line, it is important that the LEUART transmitter does not drive the line when receiving data, as this would corrupt the data on the line.
Page 626: Prs Rx Input
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.9 PRS RX Input In addition to receiving data on an external pin the LEUART can be configured to receive data directly from a PRS channel by setting RX_PRS in LEUARTn_INPUT. The PRS channel used can be selected using RX_PRS_SEL in LEUARTn_INPUT. See the PRS chapter for more details on the PRS block.
Page 627: Pulse Generator/ Pulse Extender
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.3.11 Pulse Generator/ Pulse Extender The LEUART has an optional pulse generator for the transmitter output, and a pulse extender on the receiver input. These are enabled by setting PULSEEN in LEUARTn_PULSECTRL, and with INV in LEUARTn_CTRL set, they will change the output/input format of the LEUART from NRZ to RZI as shown in Figure 19.11 LEUART - NRZ vs.
Page 628: Register Map
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LEUARTn_CTRL Control Register 0x004 LEUARTn_CMD Command Register 0x008 LEUARTn_STATUS Status Register 0x00C LEUARTn_CLKDIV Clock Control Register 0x010...
Page 629: Register Description
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5 Register Description 19.5.1 LEUARTn_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset...
Page 630 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description MPAB Multi-Processor Address-Bit Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame. Multi-Processor Mode Set to enable multi-processor mode.
Page 631 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description One stop-bit is transmitted with every frame Two stop-bits are transmitted with every frame PARITY Parity-Bit Mode Determines whether parity bits are enabled, and whether even or odd parity should be used. Value Mode Description...
Page 632: Leuartn_Cmd - Command Register (Async Reg)
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.2 LEUARTn_CMD - Command Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:8...
Page 633: Leuartn_Status - Status Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.3 LEUARTn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TXIDLE...
Page 634: Leuartn_Clkdiv - Clock Control Register (Async Reg)
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x00C Reset Access Name Name Reset Access Description...
Page 635: Leuartn_Sigframe - Signal Frame Register (Async Reg)
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description...
Page 636: Leuartn_Rxdata - Receive Buffer Data Register (Actionable Reads)
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXDATA...
Page 637: Leuartn_Txdatax - Transmit Buffer Data Extended Register (Async Reg)
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x024 Reset Access Name Name Reset...
Page 638: Leuartn_Txdata - Transmit Buffer Data Register (Async Reg)
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x028 Reset Access Name Name Reset Access...
Page 639: Leuartn_If - Interrupt Flag Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.12 LEUARTn_IF - Interrupt Flag Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
Page 640: Leuartn_Ifs - Interrupt Flag Set Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.13 LEUARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
Page 641: Leuartn_Ifc - Interrupt Flag Clear Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.14 LEUARTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
Page 642: Leuartn_Ien - Interrupt Enable Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.15 LEUARTn_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SIGF...
Page 643: Leuartn_Pulsectrl - Pulse Control Register (Async Reg)
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x03C Reset Access Name Name Reset Access Description...
Page 644: Leuartn_Freeze - Freeze Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.17 LEUARTn_FREEZE - Freeze Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REGFREEZE...
Page 645: Leuartn_Syncbusy - Synchronization Busy Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PULSECTRL...
Page 646: Leuartn_Routepen - I/O Routing Pin Enable Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TXPEN...
Page 647: Leuartn_Routeloc0 - I/O Routing Location Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 648 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXLOC...
Page 649 Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Name Reset Access Description LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 650: Leuartn_Input - Leuart Input Register
Reference Manual LEUART - Low Energy Universal Asynchronous Receiver/Transmitter 19.5.21 LEUARTn_INPUT - LEUART Input Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RXPRS...
Page 651: Timer/Wtimer - Timer/Counter
Reference Manual TIMER/WTIMER - Timer/Counter 20. TIMER/WTIMER - Timer/Counter Quick Facts What? The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms, and triggers timed actions in other peripherals. Why? Most applications have activities that need to be USART timed accurately with as little CPU intervention and energy consumption as possible.
Page 652: Features
Reference Manual TIMER/WTIMER - Timer/Counter 20.2 Features • 16/32-bit auto reload up/down counter • Dedicated 16/32-bit reload register which serves as counter maximum • 3 or 4 Compare/Capture channels • Individually configurable as either input capture or output compare/PWM • Multiple Counter modes •...
Page 653: Functional Description
Reference Manual TIMER/WTIMER - Timer/Counter • Configurable action on fault • Set outputs inactive • Clear output • Tristate output • Individual fault sources • One or two PRS signals • Debugger • Support for automatic restart • Core lockup •...
Page 654 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.1.1 Events Overflow is set when the counter value shifts from TIMERn_TOP to the next value when counting up. In up-count mode and Quadrature Decoder mode the next value is 0. In up/down-count mode, the next value is TIMERn_TOP-1. Underflow is set when the counter value shifts from 0 to the next value when counting down.
Page 655 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.1.3 Clock Source The counter can be clocked from several sources, which are all synchronized with the peripheral clock (HFPERCLK). See Figure 20.3 TIMER/WTIMER Clock Selection on page 655. Counter PRESC CLKSEL (Controlled by TIMERn_CTRL) HFPERCLK Prescaler Counter...
Page 656 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.1.8 Top Value Buffer The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB (buffer) register. When writing to the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event. Buffering ensures that the TOP value is not set below the actual count value.
Page 657 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.1.9 Quadrature Decoder Quadrature Decoding mode is used to track motion and determine both rotation direction and position. The Quadrature Decoder uses two input channels that are 90 degrees out of phase (see Figure 20.6 TIMER/WTIMER Quadrature Encoded Inputs on page 657).
Page 658 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.1.10 X2 Decoding Mode In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see Table 20.1 TIMER/WTIMER Counter Response in X2 Decoding Mode on page 658 Figure 20.8 TIMER/WTIMER X2 Decoding Mode on page 658.
Page 659: Compare/Capture Channels
Reference Manual TIMER/WTIMER - Timer/Counter 20.3.1.12 TIMER/WTIMER Rotational Position To calculate a position Figure 20.10 TIMER/WTIMER Rotational Position Equation on page 659 can be used. pos° = (CNT/X x N) x 360° Figure 20.10. TIMER/WTIMER Rotational Position Equation where X = Encoding type and N = Number of pulses per revolution. 20.3.2 Compare/Capture Channels The timer contains 3 Compare/Capture channels, which can be configured in the following modes: 1.
Page 660 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.3 Input Capture In Input Capture Mode, the counter value (TIMERn_CNT) can be captured in the Compare/Capture Register (TIMERn_CCx_CCV) (see Figure 20.12 TIMER/WTIMER Input Capture on page 660). The CCPOL bits in TIMERn_STATUS indicate the polarity of the edge that triggered the capture in TIMERn_CCx_CCV.
Page 661 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.4 Period/Pulse-Width Capture Period and/or pulse-width capture can only be possible with Channel 0 (CC0), because this is the only channel that can start and stop the timer. This can be done by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted input from either exter- nal pin or PRS, see Figure 20.13 TIMER/WTIMER Period and/or Pulse width Capture on page 661.
Page 662 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.5 Compare Each Compare/Capture channel contains a comparator which outputs a compare match if the contents of TIMERn_CCx_CCV matches the counter value, see Figure 20.14 TIMER/WTIMER Block Diagram Showing Comparison Functionality on page 662. In compare mode, each compare channel can be configured to either set, clear or toggle the output on an event (compare match, overflow or un- derflow).
Page 663 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.6 Compare Mode Registers When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Com- pare mode the output can be configured to toggle, clear or set on compare match, overflow, and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL.
Page 664 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.7 Frequency Generation (FRG) Frequency generation (see Figure 20.17 TIMER/WTIMER Up-count Frequency Generation on page 664) can be achieved in compare mode by: • Setting the counter in up-count mode • Enabling buffering of the TOP value. •...
Page 665 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.9 Up-count (Single-slope) PWM If the counter is set to up-count and the Compare/Capture channel is put in PWM mode, single slope PWM output will be generated (see Figure 20.20 TIMER/WTIMER Up-count PWM Generation on page 665).
Page 666 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.10 2x Count Mode (Up-count) When the timer is set in 2x mode, the TIMER/WTIMER will count up by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure 20.25 TIMER/WTIMER CC out in 2x mode on page 666 Clock CC Out...
Page 667 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.11 Up/Down-count (Dual-slope) PWM If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual slope PWM output will be generated Figure 20.29 TIMER/WTIMER Up/Down-count PWM Generation on page 667.The resolution (in bits) is given by Figure 20.30 TIM- ER/WTIMER Up/Down-count PWM Resolution Equation on page...
Page 668 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.2.12 2x Count Mode (Up/Down-count) When the timer is set in 2x mode, the TIMER/WTIMER will count up/down by two. This will in effect make any odd Top value be roun- ded down to the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure 20.34 TIMER/WTIMER CC out in 2x mode on page 668 Clock CC Out...
Page 669: Dead-Time Insertion Unit
Reference Manual TIMER/WTIMER - Timer/Counter 20.3.3 Dead-Time Insertion Unit Some of the timers include a Dead-Time Insertion module suitable for motor control applications. Refer to the device data sheet to check if a timer has this feature. The example settings in this section are for TIMER0, but identical settings can be used for other timers with DTI as well.
Page 670 Reference Manual TIMER/WTIMER - Timer/Counter DTFALLT DTRISET Select Original PWM (TIM0_CCx_pre) HFPERCLK Clock control Counter TIMERn Primary output (TIM0_CCx) Complementary Output (TIM0_CDTIx) Figure 20.41. TIMER/WTIMER Overview of Dead-Time Insertion Block for a Single PWM channel The DTI unit is enabled by setting DTEN in TIMER0_DTCTRL. In addition to providing the complementary outputs, the DTI unit then also overrides the compare match outputs from the timer.
Page 671 Reference Manual TIMER/WTIMER - Timer/Counter Table 20.3. DTI Output When Timer Halted DTAR DTFATS State frozen safe running running 20.3.3.1 Output Polarity The value of the primary and complementary outputs in a pair will never be set active at the same time by the DTI unit. The polarity of the outputs can be changed if this is required by the application.
Page 672 Reference Manual TIMER/WTIMER - Timer/Counter 20.3.3.2 PRS Channel as a Source A PRS channel can be used as input to the DTI module instead of the PWM output from the timer for DTI channel 0. Setting DTPRSEN in TIMER0_DTCTRL will override the source of the first DTI channel, driving TIM0_CC0 and TIM0_CDTI0, with the value on the PRS channel.
Page 673: Debug Mode
Reference Manual TIMER/WTIMER - Timer/Counter 20.3.4 Debug Mode When the CPU is halted in debug mode, the timer can be configured to either continue to run or to be frozen. This is configured in DEBUGRUN in TIMERn_CTRL. 20.3.5 Interrupts, DMA and PRS Output The timer has 3 different types of output events: •...
Page 674: Register Map
Reference Manual TIMER/WTIMER - Timer/Counter 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMERn_CTRL Control Register 0x004 TIMERn_CMD Command Register 0x008 TIMERn_STATUS Status Register 0x00C TIMERn_IF Interrupt Flag Register 0x010 TIMERn_IFS Interrupt Flag Set Register...
Page 675: Register Description
Reference Manual TIMER/WTIMER - Timer/Counter 20.5 Register Description 20.5.1 TIMERn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions RSSCOIST...
Page 676 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description Compare/Capture Channel 1 Input TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DISSYNCOUT...
Page 677 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description Quadrature Decoder Mode Selection This bit sets the mode for the quadrature decoder. Value Mode Description X2 mode selected X4 mode selected OSMEN One-shot Mode Enable Enable/disable one shot mode. SYNC Timer Start/Stop/Reload Synchronization When this bit is set, the Timer is started/stopped/reloaded by start/stop/reload commands in the other timers Value...
Page 678: Timern_Cmd - Command Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.2 TIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions STOP Stop Timer Set this bit to stop timer...
Page 679: Timern_Status - Status Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.3 TIMERn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CCPOL3 CC3 Polarity In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC3_CCV.
Page 680 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description 23:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICV3 CC3 Input Capture Valid This bit indicates that TIMERn_CC3_CCV contains a valid capture value. These bits are only used in input capture mode and are cleared when CCMODE is written to 0b00 (Off).
Page 681 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description CCVBV2 CC2 CCVB Valid This field indicates that the TIMERn_CC2_CCVB registers contain data which have not been written to TIMERn_CC2_CCV. These bits are only used in output compare/PWM mode and are cleared when CCMODE is written to 0b00 (Off).
Page 682: Timern_If - Interrupt Flag Register
Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description RUNNING Running Indicates if timer is running or not. 20.5.4 TIMERn_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3...
Page 683: Timern_Ifs - Interrupt Flag Set Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.5 TIMERn_IFS - Interrupt Flag Set Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3 Set ICBOF3 Interrupt Flag...
Page 684: Timern_Ifc - Interrupt Flag Clear Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.6 TIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3 (R)W1...
Page 685 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description (R)W1 Clear UF Interrupt Flag Write 1 to clear the UF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). (R)W1 Clear OF Interrupt Flag Write 1 to clear the OF interrupt flag.
Page 686: Timern_Ien - Interrupt Enable Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.7 TIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ICBOF3 ICBOF3 Interrupt Enable...
Page 687: Timern_Top - Counter Top Value Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.8 TIMERn_TOP - Counter Top Value Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:0 0x0000FFFF Counter Top Value These bits hold the TOP value for the counter. 20.5.9 TIMERn_TOPB - Counter Top Value Buffer Register Offset Bit Position 0x020...
Page 688: Timern_Cnt - Counter Value Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.10 TIMERn_CNT - Counter Value Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 0x00000000 Counter Value These bits hold the counter value. 20.5.11 TIMERn_LOCK - TIMER Configuration Lock Register Offset Bit Position 0x02C Reset...
Page 689: Timern_Routepen - I/O Routing Pin Enable Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CDTI2PEN...
Page 690: Timern_Routeloc0 - I/O Routing Location Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 CC3LOC...
Page 691 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16...
Page 692 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 693 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CC0LOC...
Page 694 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 695: Timern_Routeloc2 - I/O Routing Location Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 CDTI2LOC...
Page 696 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 697 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CDTI0LOC...
Page 698 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 699: Timern_Ccx_Ctrl - Cc Channel Control Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.15 TIMERn_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions FILT Digital Filter...
Page 700 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description 25:24 ICEDGE Input Capture Edge Select These bits control which edges the edge detector triggers on. The output is used for input capture and external clock input. Value Mode Description RISING Rising edges detected FALLING Falling edges detected...
Page 701 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description NONE No action on counter overflow TOGGLE Toggle output on counter overflow CLEAR Clear output on counter overflow Set output on counter overflow CMOA Compare Match Output Action Select output action on compare match. Value Mode Description...
Page 702: Timern_Ccx_Ccv - Cc Channel Value Register (Actionable Reads)
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads) Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:0 0x00000000 CC Channel Value In input capture mode, this field holds the first unread capture value. When reading this register in input capture mode, the contents of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle.
Page 703: Timern_Ccx_Ccvb - Cc Channel Buffer Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.18 TIMERn_CCx_CCVB - CC Channel Buffer Register Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:0 CCVB 0x00000000 CC Channel Value Buffer In Input Capture mode, this field holds the last capture value if the TIMERn_CCx_CCV register already contains an earlier unread capture value.
Page 704: Timern_Dtctrl - Dti Control Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.19 TIMERn_DTCTRL - DTI Control Register Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTPRSEN DTI PRS Source Enable...
Page 705 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description DTCINV DTI Complementary Output Invert Set to invert complementary outputs. DTIPOL DTI Inactive Polarity Set inactive polarity for outputs. DTDAS DTI Automatic Start-up Functionality Configure DTI restart on debugger exit. Value Mode Description NORESTART...
Page 706: Timern_Dttime - Dti Time Control Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.20 TIMERn_DTTIME - DTI Time Control Register Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 21:16 DTFALLT...
Page 707 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description silabs.com | Building a more connected world. Rev. 1.1 | 707...
Page 708: Timern_Dtfc - Dti Fault Configuration Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.21 TIMERn_DTFC - DTI Fault Configuration Register Offset Bit Position 0x0A8 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTLOCKUPFEN DTI Lockup Fault Enable...
Page 709 Reference Manual TIMER/WTIMER - Timer/Counter Name Reset Access Description PRSCH3 PRS Channel 3 selected as fault source 1 PRSCH4 PRS Channel 4 selected as fault source 1 PRSCH5 PRS Channel 5 selected as fault source 1 PRSCH6 PRS Channel 6 selected as fault source 1 PRSCH7 PRS Channel 7 selected as fault source 1 PRSCH8...
Page 710: Timern_Dtogen - Dti Output Generation Enable Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTOGCDTI2EN...
Page 711: Timern_Dtfault - Dti Fault Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.23 TIMERn_DTFAULT - DTI Fault Register Offset Bit Position 0x0B0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DTLOCKUPF DTI Lockup Fault...
Page 712: Timern_Dtfaultc - Dti Fault Clear Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions TLOCKUPFC DTI Lockup Fault Clear...
Page 713: Timern_Dtlock - Dti Configuration Lock Register
Reference Manual TIMER/WTIMER - Timer/Counter 20.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register Offset Bit Position 0x0B8 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0 LOCKKEY...
Page 714: Letimer - Low Energy Timer
Reference Manual LETIMER - Low Energy Timer 21. LETIMER - Low Energy Timer Quick Facts What? The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32768 Hz clock, the LETIMER is available in EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop.
Page 715: Functional Description
Reference Manual LETIMER - Low Energy Timer 21.3 Functional Description An overview of the LETIMER module is shown in Figure 21.1 LETIMER Overview on page 715. The LETIMER is a 16-bit down-coun- ter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_COMP0 register can optionally act as a top value for the counter.
Page 716: Top Value
Reference Manual LETIMER - Low Energy Timer 21.3.3 Top Value If COMP0TOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 acts as the top value of the timer, and LETIMERn_COMP0 is loaded into LETIMERn_CNT on timer underflow. If COMP0TOP is cleared to 0, the timer wraps around to 0xFFFF. The underflow interrupt flag UF in LETIMERn_IF is set when the timer reaches zero.
Page 717 Reference Manual LETIMER - Low Energy Timer 21.3.3.3 Free-Running Mode In free-running mode, the LETIMER acts as a regular timer and the repeat counter is disabled. When started, the timer runs until it is stopped using the STOP command bit in LETIMERn_CMD. A state machine for this mode is shown in Figure 21.2 LETIMER State Machine for Free-running Mode on page 717 Wait for positive clock edge...
Page 718 Reference Manual LETIMER - Low Energy Timer 21.3.3.4 One-shot Mode The one-shot repeat mode is the most basic repeat mode. In this mode, the repeat register LETIMERn_REP0 is decremented every time the timer underflows, and the timer stops when LETIMERn_REP0 goes from 1 to 0. In this mode, the timer counts down LETI- MERn_REP0 times, i.e.
Page 719 Reference Manual LETIMER - Low Energy Timer 21.3.3.5 Buffered Mode The Buffered repeat mode allows buffered timer operation. When started, the timer runs LETIMERn_REP0 number of times. If LETI- MERn_REP1 has been written since the last time it was used and it is nonzero, LETIMERn_REP1 is then loaded into LETI- MERn_REP0, and counting continues the new number of times.
Page 720 Reference Manual LETIMER - Low Energy Timer 21.3.3.6 Double Mode The Double repeat mode works much like the one-shot repeat mode. The difference is that, where the one-shot mode counts as long as LETIMERn_REP0 is larger than 0, the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0.
Page 721 Reference Manual LETIMER - Low Energy Timer 21.3.3.8 PRS Input Triggers The LETIMER can be configured to start, stop, and/or clear based on PRS inputs. The diagram showing the functions of the PRS input triggers is shown in Figure 21.7 LETIMER PRS Input Triggers on page 721.
Page 722: Underflow Output Action
Reference Manual LETIMER - Low Energy Timer 21.3.4 Underflow Output Action For each of the repeat registers, an underflow output action can be set. The configured output action is performed every time the coun- ter underflows while the respective repeat register is nonzero. In PWM mode, the output is similarly only changed on COMP1 match if the repeat register is nonzero.
Page 723 Reference Manual LETIMER - Low Energy Timer Initial configuration COMP0 Int. flags set UFIF UFIF UFIF UFIF UFIF UFIF LFACLK LETIMERn LETn_O0 UFOA0 = 00 LETn_O0 UFOA0 = 01 LETn_O0 UFOA0 = 10 Figure 21.8. LETIMER Simple Waveforms Output For the example in Figure 21.9 LETIMER Repeated Counting on page 723, the One-shot repeat mode has been selected, and LETI- MERn_REP0 has been written to 3.
Page 724: Prs Output
Reference Manual LETIMER - Low Energy Timer UFOA0 = 10 UFOA1 = 10 REP0 = 2 REP0 = 2 REP1 = 7 REP0 = 3 REP1 = 3 START START START LETn_O0 LETn_O1 Figure 21.10. LETIMER Dual Output 21.3.5 PRS Output The LETIMER outputs can be routed out onto the PRS system.
Page 725 Reference Manual LETIMER - Low Energy Timer 21.3.6.1 Triggered Output Generation If both LETIMERn_CNT and LETIMERn_REP0 are 0 in buffered mode, and COMP0TOP and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_COMP1 and LETIMERn_REP1 are loaded into LETIMERn_CNT and LETIMERn_REP0 respectively when the timer is started.
Page 726 Reference Manual LETIMER - Low Energy Timer 21.3.6.2 Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 21.8 LETIMER Simple Waveforms Output on page 723, but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous.
Page 727: Register Access
Reference Manual LETIMER - Low Energy Timer Note: Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 21.12 LETIMER Continuous Operation on page 726 assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 21.13 LETIMER LETIMERn_CNT Not Initialized to 0 on page 727 shows an example where the LETIMER is started while LETIMERn_CNT is nonzero.
Page 728: Register Map
Reference Manual LETIMER - Low Energy Timer 21.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMERn_CTRL Control Register 0x004 LETIMERn_CMD Command Register 0x008 LETIMERn_STATUS Status Register 0x00C LETIMERn_CNT Counter Value Register 0x010 LETIMERn_COMP0 Compare Value Register 0...
Page 729: Register Description
Reference Manual LETIMER - Low Energy Timer 21.5 Register Description 21.5.1 LETIMERn_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset Access Description...
Page 730 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description UFOA1 Underflow Output Action 1 Defines the action on LETn_O1 on a LETIMER underflow. Value Mode Description NONE LETn_O1 is held at its idle value as defined by OPOL1 TOGGLE LETn_O1 is toggled on CNT underflow PULSE...
Page 731: Letimern_Cmd - Command Register
Reference Manual LETIMER - Low Energy Timer 21.5.2 LETIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CTO1 Clear Toggle Output 1...
Page 732: Letimern_Cnt - Counter Value Register
Reference Manual LETIMER - Low Energy Timer 21.5.4 LETIMERn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:0...
Page 733: Letimern_Comp1 - Compare Value Register 1 (Async Reg)
Reference Manual LETIMER - Low Energy Timer 21.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16...
Page 734: Letimern_Rep1 - Repeat Counter Register 1 (Async Reg)
Reference Manual LETIMER - Low Energy Timer 21.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8...
Page 735: Letimern_Ifs - Interrupt Flag Set Register
Reference Manual LETIMER - Low Energy Timer 21.5.10 LETIMERn_IFS - Interrupt Flag Set Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REP1...
Page 736: Letimern_Ifc - Interrupt Flag Clear Register
Reference Manual LETIMER - Low Energy Timer 21.5.11 LETIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REP1...
Page 737: Letimern_Ien - Interrupt Enable Register
Reference Manual LETIMER - Low Energy Timer 21.5.12 LETIMERn_IEN - Interrupt Enable Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions REP1...
Page 738: Letimern_Routepen - I/O Routing Pin Enable Register
Reference Manual LETIMER - Low Energy Timer 21.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUT1PEN...
Page 739: Letimern_Routeloc0 - I/O Routing Location Register
Reference Manual LETIMER - Low Energy Timer 21.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:8...
Page 740 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUT0LOC...
Page 741 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 742: Letimern_Prssel - Prs Input Select Register
Reference Manual LETIMER - Low Energy Timer 21.5.16 LETIMERn_PRSSEL - PRS Input Select Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 27:26...
Page 743 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description FALLING Falling edge of selected PRS input can start the LETIMER BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 17:16 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 744 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRSSTARTSEL PRS Start Select Determines which PRS input can start the LETIMER. Value Mode Description...
Page 745: Cryotimer - Ultra Low Energy Timer/Counter
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22. CRYOTIMER - Ultra Low Energy Timer/Counter Quick Facts What? The CRYOTIMER is a timer capable of providing wakeup events/interrupts after deterministic intervals in all energy modes, including EM4. Why? CRYOTIMER The CRYOTIMER enables the chip to remain in the lowest energy modes for long durations, while keep- ing track of time and being able to wake up at regu- lar intervals, all with an absolute minimum current...
Page 746: Block Diagram
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.3.1 Block Diagram An overview of the CRYOTIMER is shown in Figure 22.1 CRYOTIMER Block Overview on page 746. LFXO CRYOCLK LFRCO Prescaler Counter ULFRCO Edge Detector Interrupt/ Wakeup Event OSCSEL PRESC PERIODSEL Figure 22.1.
Page 747: Operation
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.3.2 Operation The desired low frequency oscillator for the CRYOTIMER operation can be selected by using OSCSEL in CRYOTIMER_CTRL. The selection must be made before enabling the CRYOTIMER, and it must be ensured that the selected oscillator is ready. This can be checked by observing LFXORDY or LFRCORDY (depending upon the oscillator selection) in CMU_STATUS.
Page 748: Register Map
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CRYOTIMER_CTRL Control Register 0x004 CRYOTIMER_PERIODSEL Interrupt Duration 0x008 CRYOTIMER_CNT Counter Value 0x00C CRYOTIMER_EM4WUEN Wake Up Enable 0x010 CRYOTIMER_IF...
Page 749: Register Description
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5 Register Description 22.5.1 CRYOTIMER_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PRESC...
Page 750: Cryotimer_Periodsel - Interrupt Duration
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5.2 CRYOTIMER_PERIODSEL - Interrupt Duration Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIODSEL...
Page 751: Cryotimer_Cnt - Counter Value
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter Name Reset Access Description Wakeup event after 8M Pre-scaled clock cycles. Wakeup event after 16M Pre-scaled clock cycles. Wakeup event after 32M Pre-scaled clock cycles. Wakeup event after 64M Pre-scaled clock cycles. Wakeup event after 128M Pre-scaled clock cycles.
Page 752: Cryotimer_If - Interrupt Flag Register
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5.5 CRYOTIMER_IF - Interrupt Flag Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIOD...
Page 753: Cryotimer_Ifc - Interrupt Flag Clear Register
Reference Manual CRYOTIMER - Ultra Low Energy Timer/Counter 22.5.7 CRYOTIMER_IFC - Interrupt Flag Clear Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions PERIOD...
Page 754: Vdac - Digital To Analog Converter
Reference Manual VDAC - Digital to Analog Converter 23. VDAC - Digital to Analog Converter Quick Facts What? The VDAC is designed for low energy consumption, but can also provide very good performance. It can convert digital values to analog signals at up to 500 kilo samples/second with 12-bit accuracy.
Page 755: Features
Reference Manual VDAC - Digital to Analog Converter 23.2 Features • 500 ksamples/s operation • Two single ended output channels • Can be combined into one differential output • Integrated prescaler with division factor selectable between 1-128 • Selectable voltage reference •...
Page 756: Power Supply
Reference Manual VDAC - Digital to Analog Converter OPA0_OUT OPA0 VDAC0_OUT0 CH0DATA Ch 0 MAINOUTEN VDAC0_OUT0ALTx ALTOUTEN, ALTOUTPADEN APORT APORTOUTEN OPA1_OUT OPA1 VDAC0_OUT1 CH1DATA Ch 1 MAINOUTEN VDAC0_OUT1ALTx 1.25 V Low Noise ALTOUTEN, 2.5 V Low Noise ALTOUTPADEN 1.25 V APORT 2.5 V APORTOUTEN...
Page 757: Conversions
Reference Manual VDAC - Digital to Analog Converter 23.3.4 Conversions The VDAC consists of two channels (channel 0 and 1) with separate 12-bit data registers (VDACn_CH0DATA and VDACn_CH1DATA). These can be used to produce two independent single ended outputs or the channel 0 register can be used to drive both outputs in differential mode.
Page 758: Warmup Time And Initial Conversion
Reference Manual VDAC - Digital to Analog Converter • External Pin 23.3.6 Warmup Time and Initial Conversion When a channel is first enabled it needs to warm up. This is performed automatically during the first conversion. The time required to warm up depends on the programmed DRIVESTRENGTH field in VDACn_OPAx_CTRL.
Page 759: Async Mode
Reference Manual VDAC - Digital to Analog Converter the data is written in 2’s complement form with the MSB of the 12-bit value being the signed bit. The output voltage can be calculated using Figure 23.3 VDAC Differential Output Voltage on page 759: x CH0DATA/2047 VDACn_OUT1...
Page 760: Sine Generation Mode
Reference Manual VDAC - Digital to Analog Converter 4. Set up a DMA transfer from a buffer in RAM to CHxDATA 5. Set CONVMODE to CONTINUOUS 23.3.13 Sine Generation Mode The VDAC contains an automatic sine-generation mode, which is enabled by setting the SINEMODE bit in VDACn_CTRL. In this mode, the VDAC data is overridden with a conversion data taken from a sine lookup table.
Page 761: Prs Outputs
Reference Manual VDAC - Digital to Analog Converter 23.3.14.3 Overflow/Underflow If CHxDATA is written to while CHxBL is cleared, the channel overflow flag (CHxOF) will be set. If a new conversion is triggered (e.g. via PRS) before data is written to CHxDATA (CHxDATA is empty) the channel underflow flag (CHxUF) will be set. 23.3.14.4 EM2/3 Sleep Error The VDAC can only operate in EM2/3 when DACCLKMODE is set to ASYNC.
Page 762: Warmup Mode
Reference Manual VDAC - Digital to Analog Converter e = abs(V * 0.8) - 1) Figure 23.7. Calibration Error where V is the measured voltage at the pin and V is the reference voltage. Note that even if only CH1 is going to be used, the full calibration procedure should be followed. It is permissible to skip CH1 calibration if only CH0 is used.
Page 763: Register Map
Reference Manual VDAC - Digital to Analog Converter 23.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 VDACn_CTRL Control Register 0x004 VDACn_STATUS Status Register 0x008 VDACn_CH0CTRL Channel 0 Control Register 0x00C VDACn_CH1CTRL Channel 1 Control Register...
Page 764: Register Description
Reference Manual VDAC - Digital to Analog Converter 23.5 Register Description 23.5.1 VDACn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description DACCLKMODE Clock Mode Selects DAC clock source from synchronous or asynchronous - with respect to Peripheral Clock - clock source Value Mode Description...
Page 765 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description 64CYCLES All channels with enabled refresh are refreshed every 64 DAC_CLK cy- cles Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 22:16...
Page 766 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description Sine mode disabled. Sine reset to 0 degrees Sine mode enabled Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DIFF Differential Mode...
Page 767: Vdacn_Status - Status Register
Reference Manual VDAC - Digital to Analog Converter 23.5.2 VDACn_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OPA1OUTVALID...
Page 768 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description CH1WARM Channel 1 Warm This bit is set when channel 1 is warm. CH0WARM Channel 0 Warm This bit is set when channel 0 is warm. CH1BL Channel 1 Buffer Level This bit is set when there is space for new data in CH1DATA.
Page 769: Vdacn_Ch0Ctrl - Channel 0 Control Register
Reference Manual VDAC - Digital to Analog Converter 23.5.3 VDACn_CH0CTRL - Channel 0 Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
Page 770 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description REFRESH Channel 0 is triggered by Refresh timer SWPRS Channel 0 is triggered by CH0DATA/COMBDATA write or PRS input SWREFRESH Channel 0 is triggered by CH0DATA/COMBDATA write or Refresh timer LESENSE Channel 0 is triggered by LESENSE Reserved...
Page 771: Vdacn_Ch1Ctrl - Channel 1 Control Register
Reference Manual VDAC - Digital to Analog Converter 23.5.4 VDACn_CH1CTRL - Channel 1 Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:12...
Page 772 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description REFRESH Channel 1 is triggered by Refresh timer SWPRS Channel 1 is triggered by CH1DATA/COMBDATA write or PRS input SWREFRESH Channel 1 is triggered by CH1DATA/COMBDATA write or Refresh timer LESENSE Channel 1 is triggered by LESENSE Reserved...
Page 773: Vdacn_Cmd - Command Register
Reference Manual VDAC - Digital to Analog Converter 23.5.5 VDACn_CMD - Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OPA1DIS...
Page 774: Vdacn_If - Interrupt Flag Register
Reference Manual VDAC - Digital to Analog Converter 23.5.6 VDACn_IF - Interrupt Flag Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OPA1OUTVALID...
Page 775 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description CH0BL Channel 0 Buffer Level Interrupt Flag Indicates space available in CH0DATA. CH1UF Channel 1 Data Underflow Interrupt Flag Indicates channel 1 data underflow. CH0UF Channel 0 Data Underflow Interrupt Flag Indicates channel 0 data underflow.
Page 776: Vdacn_Ifs - Interrupt Flag Set Register
Reference Manual VDAC - Digital to Analog Converter 23.5.7 VDACn_IFS - Interrupt Flag Set Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OPA1OUTVALID...
Page 777 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description CH0UF Set CH0UF Interrupt Flag Write 1 to set the CH0UF interrupt flag CH1OF Set CH1OF Interrupt Flag Write 1 to set the CH1OF interrupt flag CH0OF Set CH0OF Interrupt Flag Write 1 to set the CH0OF interrupt flag CH1CD Set CH1CD Interrupt Flag...
Page 778: Vdacn_Ifc - Interrupt Flag Clear Register
Reference Manual VDAC - Digital to Analog Converter 23.5.8 VDACn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OPA1OUTVALID...
Page 779 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description 14:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CH1UF (R)W1 Clear CH1UF Interrupt Flag Write 1 to clear the CH1UF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.).
Page 780: Vdacn_Ien - Interrupt Enable Register
Reference Manual VDAC - Digital to Analog Converter 23.5.9 VDACn_IEN - Interrupt Enable Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OPA1OUTVALID...
Page 781: Vdacn_Ch0Data - Channel 0 Data Register
Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description CH0BL CH0BL Interrupt Enable Enable/disable the CH0BL interrupt CH1UF CH1UF Interrupt Enable Enable/disable the CH1UF interrupt CH0UF CH0UF Interrupt Enable Enable/disable the CH0UF interrupt CH1OF CH1OF Interrupt Enable Enable/disable the CH1OF interrupt CH0OF CH0OF Interrupt Enable...
Page 782: Vdacn_Ch1Data - Channel 1 Data Register
Reference Manual VDAC - Digital to Analog Converter 23.5.11 VDACn_CH1DATA - Channel 1 Data Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 11:0...
Page 783: Vdacn_Cal - Calibration Register
Reference Manual VDAC - Digital to Analog Converter 23.5.13 VDACn_CAL - Calibration Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 19:16...
Page 784: Vdacn_Opax_Aportreq - Operational Amplifier Aport Request Status Register
Reference Manual VDAC - Digital to Analog Converter 23.5.14 VDACn_OPAx_APORTREQ - Operational Amplifier APORT Request Status Register Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YREQ...
Page 785: 23.5.15 Vdacn_Opax_Aportconflict - Operational Amplifier Aport Conflict Status Register
Reference Manual VDAC - Digital to Analog Converter 23.5.15 VDACn_OPAx_APORTCONFLICT - Operational Amplifier APORT Conflict Status Register Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YCONFLICT 0...
Page 786: Vdacn_Opax_Ctrl - Operational Amplifier Control Register
Reference Manual VDAC - Digital to Analog Converter 23.5.16 VDACn_OPAx_CTRL - Operational Amplifier Control Register Offset Bit Position 0x0A8 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTYMASTER-...
Page 787 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description OUTVALID Outvalid status available on PRS. Outvalid status indicates that opamp output is settled externally at the load. 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 13:10...
Page 788 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description Value Mode Description FULL Select this for full output driving strength. HALF Select this for half output driving strength. HCMDIS High Common Mode Disable Set to disable high common mode. Disables rail-to-rail on input, while output still remains rail-to-rail. The input voltage to the opamp while HCM is disabled is restricted between VSS and VDD-1.2V.
Page 789: Vdacn_Opax_Timer - Operational Amplifier Timer Control Register
Reference Manual VDAC - Digital to Analog Converter 23.5.17 VDACn_OPAx_TIMER - Operational Amplifier Timer Control Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 25:16...
Page 790: Vdacn_Opax_Mux - Operational Amplifier Mux Configuration Register
Reference Manual VDAC - Digital to Analog Converter 23.5.18 VDACn_OPAx_MUX - Operational Amplifier Mux Configuration Register Offset Bit Position 0x0B0 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 26:24...
Page 791 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description OPANEXT Set for NEXTOUT(x-1) input NEGPAD NEG pad connected POSPAD POS pad connected COMPAD Neg pad of OPA0 connected. Direct input to support common refer- ence. CENTER OPA0 and OPA1 Resmux connected to form fully differential instrumen- tation amplifier.
Page 792 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description Mode Value Description APORT1XCH0 Select APORT1XCH0 APORT1XCH2 Select APORT1XCH2 APORT1XCH4 Select APORT1XCH4 ..APORT1XCH30 Select APORT1XCH30 APORT2XCH1 Select APORT2XCH1 APORT2XCH3 Select APORT2XCH3 APORT2XCH5 Select APORT2XCH5 ..APORT2XCH31 Select APORT2XCH30 APORT3XCH0 Select APORT3XCH0 APORT3XCH2...
Page 793: Vdacn_Opax_Out - Operational Amplifier Output Configuration Register
Reference Manual VDAC - Digital to Analog Converter 23.5.19 VDACn_OPAx_OUT - Operational Amplifier Output Configuration Register Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 23:16...
Page 794 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description ALTOUTPADEN 0x00 OPAx Output Enable Value Set to enable output, clear to disable output OUT ENABLE VALUE Description OUT0 xxxx1 Alternate Output 0 OUT1 xxx1x Alternate Output 1 OUT2 xx1xx Alternate Output 2...
Page 795: Vdacn_Opax_Cal - Operational Amplifier Calibration Register
Reference Manual VDAC - Digital to Analog Converter 23.5.20 VDACn_OPAx_CAL - Operational Amplifier Calibration Register Offset Bit Position 0x0B8 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:26...
Page 796 Reference Manual VDAC - Digital to Analog Converter Name Reset Access Description Compensation Cap Cm1 Trim Value Program with value obtained from Device Information page (DEVINFO_OPAxCALn) depending on OPAMP number and chosen DRIVESTRENGTH. silabs.com | Building a more connected world. Rev.
Page 797: Opamp - Operational Amplifier
Reference Manual OPAMP - Operational Amplifier 24. OPAMP - Operational Amplifier Quick Facts What? The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of stand- ard opamp application areas. With flexible gain and interconnection built-in, they can be configured to support multiple common opamp functions.
Page 798: Functional Description
Reference Manual OPAMP - Operational Amplifier • Output status to PRS 24.3 Functional Description The 2 opamps can be configured to perform various opamp functions through a network of muxes. An overview of the opamps are shown in Figure 24.1 OPAMP System Overview on page 798.
Page 799: Opamp Configuration
Reference Manual OPAMP - Operational Amplifier POSSEL POS0 DAC0CH0 OPA0TAP APORT1X APORT2X APORT3X APORT4X Main output OPA0 Alternative output network NEG0 Aport output NEXTOUT0 APORT1Y APORT2Y APORT3Y APORT4Y NEGSEL UNITYGAIN OPA0TAP RESSEL GAIN3X NEG0 CENTER01 RESINMUX POS1 POSSEL DAC0CH1 NEXTOUT0 OPA1TAP APORT1X APORT2X...
Page 800 Reference Manual OPAMP - Operational Amplifier • VDACn_OPAx_CTRL • VDACn_OPAx_TIMER • VDACn_OPAx_MUX 24.3.1.1 Enable Sources Opamp can be enabled either with software or PRS. The default source is software. Setting PRSEN to 1 in VDACn_OPAx_CTRL ena- bles PRS mode. In PRS mode, opamp has two options, which are selectable with PRSMODE in VDACn_OPAx_CTRL. If PRSMODE is configured to TIMED, opamp is turned on on the positive edge of PRS and stays on until PRS goes low.
Page 801 Reference Manual OPAMP - Operational Amplifier 24.3.1.6 I/O Pin Considerations The maximum usable analog signal that can be applied to external opamp inputs (or seen on external opamp outputs) depends on several factors: whether the signal is routed through the APORT, whether High Linearity mode is used, whether overvoltage is enabled, and on the IOVDD/AVDD supply voltages, as shown in the Table 24.3 Maximum Usable IO Voltage on page 801 table.
Page 802 Reference Manual OPAMP - Operational Amplifier APORT Output APORT Output APORTOUTSEL APORTOUTSEL APORT1Y APORT1Y APORT2Y APORT2Y APORT3Y APORT3Y APORT4Y APORT4Y Main Output Main Output MAINOUTEN MAINOUTEN OPA0 OPA1 NEXTOUT0 NEXTOUT1 Alternative Output Alternative Output network network OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3...
Page 803: Interrupts And Prs Output
Reference Manual OPAMP - Operational Amplifier 24.3.1.10 Offset Calibration Each opamp has a calibration register, VDACn_OPAx_CAL, where calibration values for both offset and gain correction can be written. The required calibration settings depend on the chosen DRIVESTRENGTH. The default calibration settings stored in VDACn_OPAx_CAL are for DRIVESTRENGTH=2.
Page 804 Reference Manual OPAMP - Operational Amplifier Table 24.4. General Opamp Mode Configuration OPA Bitfields OPA Configuration OPAx POSSEL POSPADx, APORT[1-4]X OPAx NEGSEL OPATAP, UG, NEGPADx, APORT[1-4]Y OPAx RESINMUX NEXTOUT, POSPADx, NEGPADx, VSS 24.3.4.2 Voltage Follower Unity Gain In this mode, the unity gain feedback path is selected for the negative input by setting the NEGSEL bit-field to UG in the VDACn_OPAx_MUX register as shown in Figure 24.4 Voltage Follower Unity Gain Overview on page 804.
Page 805 Reference Manual OPAMP - Operational Amplifier Table 24.6. Inverting Input PGA Configuration OPA Bitfields OPA Configuration OPAx POSSEL POSPADx, APORT[1-4]X OPAx NEGSEL OPATAP OPAx RESINMUX NEXTOUT, NEGPADx, POSPADx 24.3.4.4 Non-inverting PGA Figure 24.6 Non-inverting PGA Overview on page 805 shows the non-inverting input configuration. In this mode, the negative input is connected to the resistor ladder by setting the NEGSEL bit-field to OPATAP in VDACn_OPAx_MUX.
Page 806 Reference Manual OPAMP - Operational Amplifier POS2 VOUT3=-(VOUT2-POS3) x R2/R1 + POS3 POS1 VOUT2=-(VOUT1-POS1) x R2/R1 + POS1 POS0 VOUT1=-(VIN-POS0) x R2/R1 + POS0 Figure 24.7. Cascaded Inverting PGA Overview Table 24.8 Cascaded Inverting PGA Configuration on page 806 shows cascaded non-inverting PGA with OPA0,OPA1 and OPA2. The output from OPA0 is connected to OPA1 to create the second stage by setting the RESINMUX field to OPANEXT in VDACn_OPA1_MUX.
Page 807 Reference Manual OPAMP - Operational Amplifier VOUT1=VIN(1+ R2/R1) VOUT2=VIN(1+ R2/R1) VOUT3=VIN(1+ R2/R1) Figure 24.8. Cascaded Non-inverting PGA Overview Table 24.9 Cascaded Non-inverting PGA Configuration on page 807 shows cascaded non-inverting PGA with OPA0,OPA1 and OPA2. When cascaded, the positive input on OPA0 is configured by the OPA0 POSSEL bit-field in VDACn_OPA0_MUX. The output from OPA0 is connected to OPA1 to create the second stage by setting the POSSEL field to OPANEXT in VDACn_OPA1_MUX.
Page 808 Reference Manual OPAMP - Operational Amplifier OPA1 VDIFF=(V2-V1)R2/R1 OPA0 OPA2 VDIFF=(V2-V1)R2/R1 OPA1 Figure 24.9. Two Op-amp Differential Amplifier Overview Table 24.10. OPA0/OPA1 Differential Amplifier Configuration OPA Bitfields OPA Configuration OPA0 POSSEL POSPAD0, APORT[1-4]X OPA0 NEGSEL OPA0 RESINMUX DISABLE OPA1 POSSEL POSPAD1, APORT[1-4]X OPA1 NEGSEL...
Page 809 Reference Manual OPAMP - Operational Amplifier OPA0 VOUT OPA2 VOUT=(V2-V1)R2/R1 OPA1 Figure 24.10. Three Op-amp Differential Amplifier Overview The gain for the Three Opamp Differential Amplifier is determined by the combination of the gain settings of OPA0 and OPA2. Gain values of 1/3, 1 and 3, are available and programmed as shown in the table below.
Page 810: Opamp Vdac Combination
Reference Manual OPAMP - Operational Amplifier VOUT OPA0 OPA1 VOUT Figure 24.11. Instrumentaion Amplifier Overview 24.3.4.10 Common Reference It is possible to configure all opamps to have a common reference by setting the RESINMUX to COMPAD in VDACn_OPAx_MUX. When RESINMUX of all opamps is set to COMPAD mode, the NEGPAD input of OPA0 is used. 24.3.4.11 Dual Buffer ADC Driver It is possible to use any two of the opamps to form a Dual Buffer ADC driver as shown in Figure 24.12 Dual Buffer ADC Driver Overview...
Page 811: Register Map
Reference Manual OPAMP - Operational Amplifier 24.4 Register Map The register map of the opamp can be found in 23.4 Register Map in the VDAC chapter. 24.5 Register Description The register description of the opamp can be found in 23.5 Register Description in the VDAC chapter.
Page 812: Acmp - Analog Comparator
Reference Manual ACMP - Analog Comparator 25. ACMP - Analog Comparator Quick Facts What? The ACMP (Analog Comparator) compares two ana- log signals and returns a digital value telling which is greater. Why? Applications often do not need to know the exact value of an analog signal, only if it has passed a cer- tain threshold.
Page 813: Features
Reference Manual ACMP - Analog Comparator 25.2 Features • Up to 160 selectable external I/O inputs for both positive and negative inputs • Up to 48 I/O can be used as a dividable reference • 5 selectable internal inputs • VDAC channel 0 voltage as a reference •...
Page 814: Functional Description
Reference Manual ACMP - Analog Comparator 25.3 Functional Description An overview of the ACMP is shown in Figure 25.1 ACMP Overview on page 814 POSSEL VADIV VBDIV Warmup Interrupt Warm-up ACMPACT Counter VDAC0 channel 0 / OPA0 VDAC0 channel 1 / OPA1 Dedicated APORT0 APORT1...
Page 815: Warm-Up Time
Reference Manual ACMP - Analog Comparator 25.3.2 Warm-up Time The analog comparator is enabled by setting the EN bit in ACMPn_CTRL. The comparator requires some time to stabilize after it is enabled. This time period is called the warm-up time. The warm-up period is self-timed and will complete within 5µs after EN is set. During warm-up and when the comparator is disabled, the output level of the comparator is set to the value of the INACTVAL bit in ACMPn_CTRL.
Page 816: Hysteresis
Reference Manual ACMP - Analog Comparator 25.3.4 Hysteresis When the hysteresis level is set to a non-zero value, the digital output will not toggle until the positive input voltage is at a voltage equal to the hysteresis level above or below the negative input voltage (see Figure 25.3 Hysteresis on page 816 ).
Page 817: Input Pin Considerations
Reference Manual ACMP - Analog Comparator 25.3.5 Input Pin Considerations For external ACMP inputs routed through the APORT, the maximum supported analog input voltage will be limited to the MIN(V , IOVDD) (where V is selected by the PWRSEL bitfield in ACMPn_CTRL). Note that pins configured as ACMP ACMPVDD ACMPVDD inputs should disable OVT (by setting the corresponding GPIO_Px_OVTDIS bit) to reduce any potential distortion introduced by the...
Page 818: Capacitive Sense Mode
Reference Manual ACMP - Analog Comparator 25.3.7 Capacitive Sense Mode The analog comparator includes specialized hardware for capacitive sensing of passive push buttons. Such buttons are traces on the PCB laid out in a way that creates a parasitic capacitor between the button and the ground node. Because a human finger will have a small intrinsic capacitance to ground, the capacitance of the button will increase when the button is touched.
Page 819 Reference Manual ACMP - Analog Comparator Voltage VADIV1 VADIV Divider VADIV0 voltage ACMPn_HYSTERESIS0.VADIV ACMPn_HSYTERESIS1.VADIV time ACMPOUT Figure 25.5. Capacitive Sensing Setup silabs.com | Building a more connected world. Rev. 1.1 | 819...
Page 820: Interrupts And Prs Output
Reference Manual ACMP - Analog Comparator 25.3.8 Interrupts and PRS Output The analog comparator includes an edge triggered interrupt flag (EDGE in ACMPn_IF). If either IRISE and/or IFALL in ACMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively. An interrupt request will be sent if the EDGE interrupt flag in ACMPn_IF is set and enabled through the EDGE bit in ACMPn_IEN.
Page 821: External Override Interface
Reference Manual ACMP - Analog Comparator 25.3.12 External Override Interface The ACMP can be controlled by an external module, for instance LESENSE. In this mode, the external module will take control of the positive input mux control signal, which is normally controlled by ACMP_INPUTSEL_POSSEL. Only the APORTs are selectable for the positive input mux in this mode.
Page 822: Register Description
Reference Manual ACMP - Analog Comparator 25.5 Register Description 25.5.1 ACMPn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description FULLBIAS Full Bias Current Set this bit to 1 for full bias current. See the data sheet for details. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 823 Reference Manual ACMP - Analog Comparator Name Reset Access Description LTVDDDIV2 Setting when the input will always be less than ACMPVDD/2. 17:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions ACCURACY ACMP Accuracy Mode Select between low and high accuracy mode of the comparator.
Page 824 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORTXMASTER- APORT Bus X Master Disable Determines if the ACMP will request the APORT X bus selected by POSSEL or NEGSEL. This bit allows multiple APORT connected devices to monitor the same APORT bus simultaneously by allowing the ACMP to not master the selected bus. When 1, the determination is expected to be from another peripheral, and the ACMP only passively looks at the bus.
Page 825: Acmpn_Inputsel - Input Selection Register
Reference Manual ACMP - Analog Comparator 25.5.2 ACMPn_INPUTSEL - Input Selection Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 30:28 CSRESSEL...
Page 826 Reference Manual ACMP - Analog Comparator Name Reset Access Description VBSEL VB Selection Select the input for the VB Divider Value Mode Description 1V25 1.25V 2.50V 21:16 VASEL 0x00 VA Selection Select the input for the VA Divider Mode Value Description ACMPVDD APORT2YCH0...
Page 827 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT1XCH0 0x20 APORT1X Channel 0 APORT1YCH1 0x21 APORT1Y Channel 1 APORT1XCH2 0x22 APORT1X Channel 2 APORT1YCH3 0x23 APORT1Y Channel 3 APORT1XCH4 0x24 APORT1X Channel 4 APORT1YCH5 0x25 APORT1Y Channel 5 .
Page 828 Reference Manual ACMP - Analog Comparator Name Reset Access Description DACOUT1 0xf3 DAC Channel 1 Output 0xfb Low-Power Sampled Voltage VBDIV 0xfc Divided VB Voltage VADIV 0xfd Divided VA Voltage 0xfe ACMPVDD as selected via PWRSEL 0xff POSSEL 0x00 Positive Input Select Select positive input.
Page 829 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT3XCH0 0x60 APORT3X Channel 0 APORT3YCH1 0x61 APORT3Y Channel 1 APORT3XCH2 0x62 APORT3X Channel 2 APORT3YCH3 0x63 APORT3Y Channel 3 APORT3XCH4 0x64 APORT3X Channel 4 APORT3YCH5 0x65 APORT3Y Channel 5 .
Page 830: Acmpn_Status - Status Register
Reference Manual ACMP - Analog Comparator 25.5.3 ACMPn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EXTIFACT External Override Interface Active...
Page 831: Acmpn_If - Interrupt Flag Register
Reference Manual ACMP - Analog Comparator 25.5.4 ACMPn_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT APORT Conflict Interrupt Flag...
Page 832: Acmpn_Ifc - Interrupt Flag Clear Register
Reference Manual ACMP - Analog Comparator 25.5.6 ACMPn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT...
Page 833: Acmpn_Ien - Interrupt Enable Register
Reference Manual ACMP - Analog Comparator 25.5.7 ACMPn_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT APORTCONFLICT Interrupt Enable...
Page 834: Acmpn_Aportreq - Aport Request Status Register
Reference Manual ACMP - Analog Comparator 25.5.8 ACMPn_APORTREQ - APORT Request Status Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YREQ...
Page 835: Acmpn_Aportconflict - Aport Conflict Status Register
Reference Manual ACMP - Analog Comparator 25.5.9 ACMPn_APORTCONFLICT - APORT Conflict Status Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YCONFLICT 0...
Page 836 Reference Manual ACMP - Analog Comparator Name Reset Access Description APORT0XCONFLICT 0 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral Reports if the bus connected to APORT0X is is also being requested by another peripheral silabs.com | Building a more connected world.
Page 837: Acmpn_Hysteresis0 - Hysteresis 0 Register
Reference Manual ACMP - Analog Comparator 25.5.10 ACMPn_HYSTERESIS0 - Hysteresis 0 Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 DIVVB...
Page 838: Acmpn_Hysteresis1 - Hysteresis 1 Register
Reference Manual ACMP - Analog Comparator 25.5.11 ACMPn_HYSTERESIS1 - Hysteresis 1 Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 29:24 DIVVB...
Page 839: Acmpn_Routepen - I/O Routing Pine Enable Register
Reference Manual ACMP - Analog Comparator 25.5.12 ACMPn_ROUTEPEN - I/O Routing Pine Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUTPEN...
Page 840: Acmpn_Routeloc0 - I/O Routing Location Register
Reference Manual ACMP - Analog Comparator 25.5.13 ACMPn_ROUTELOC0 - I/O Routing Location Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions OUTLOC...
Page 841 Reference Manual ACMP - Analog Comparator Name Reset Access Description LOC23 Location 23 LOC24 Location 24 LOC25 Location 25 LOC26 Location 26 LOC27 Location 27 LOC28 Location 28 LOC29 Location 29 LOC30 Location 30 LOC31 Location 31 silabs.com | Building a more connected world. Rev.
Page 842: Acmpn_Extifctrl - External Override Interface Control
Reference Manual ACMP - Analog Comparator 25.5.14 ACMPn_EXTIFCTRL - External Override Interface Control Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTSEL...
Page 843 Reference Manual ACMP - Analog Comparator Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Enable External Interface Set to enable an external module, like LESENSE, to control the ACMP silabs.com | Building a more connected world.
Page 844: Adc - Analog To Digital Converter
Reference Manual ADC - Analog to Digital Converter 26. ADC - Analog to Digital Converter Quick Facts What? The ADC is used to convert analog signals into a digital representation and features low-power, auton- omous operation. Why? In many applications there is a need to measure an- alog signals and record them in a digital representa- tion, without exhausting the energy source.
Page 845: Features
Reference Manual ADC - Analog to Digital Converter 26.2 Features • Programmable resolution (6/8/12-bit) • 13 conversion clock cycles for a 12-bit conversion • Maximum 1 Msps @ 12-bit • Maximum 1.6 Msps @ 6-bit • Configurable acquisition time • Externally controllable conversion start time using PRS in TIMED mode •...
Page 846: Functional Description
Reference Manual ADC - Analog to Digital Converter • Support for offset and gain calibration • Interrupt generation and/or DMA request when • Programmable number of converted data available in the single FIFO (also generates DMA request) • Programmable number of converted data available in the scan FIFO (also generates DMA request) •...
Page 847: Clock Selection
Reference Manual ADC - Analog to Digital Converter 26.3.1 Clock Selection The ADC logic is partitioned into two clock domains: HFPERCLK and ADC_CLK. The HFPERCLK domain contains the register inter- face logic, APORT request logic and portions of FIFO read logic. The HFPERCLK is the default clock for the ADC peripheral. The rest of the ADC is clocked by the ADC_CLK domain.
Page 848: Conversions
Reference Manual ADC - Analog to Digital Converter 26.3.2 Conversions A conversion consists of two phases: acquisition and approximation. The input is sampled in the acquisition phase before it is converted to digital representation during the approximation phase. The acquisition time can be configured independently for scan sequence and single channel conversions (see 26.3.3 ADC Modes) by setting AT in ADCn_SINGLECTRL/ADCn_SCANCTRL.
Page 849 Reference Manual ADC - Analog to Digital Converter 26.3.3.2 Scan Mode Scan mode is used to perform conversions across multiple channels, sweeping a set of selected inputs in a sequence. The configura- tion of scan mode is done in the ADCn_SCANCTRL and ADCn_SCANCTRLX registers. It has similar controls and data read mecha- nisms to single channel mode.
Page 850: Warm-Up Time
Reference Manual ADC - Analog to Digital Converter 26.3.4 Warm-up Time After power-on, the ADC requires some time for internal bias currents and references to settle prior to starting a conversion. This time period is called the warm-up time. Warm-up timing is performed by hardware. Software must program the number of ADC_CLK cycles required to count at least 1 µs in the TIMEBASE field of the ADCn_CTRL register.
Page 851: Power Supply
Reference Manual ADC - Analog to Digital Converter ADC standby/ slowacc ADC warm-up ADC conversion WARMUPMODE Conversion trigger Conversion trigger ADC warmed up waiting for trigger Power NORMAL 5 µs Time 1 µs Power KEEPINSTANDBY/ KEEPINSLOWACC 5 µs 5 µs Time 1 µs Power...
Page 852: Input Selection
Reference Manual ADC - Analog to Digital Converter 26.3.7 Input Selection The ADC samples and converts the analog voltage differential at its positive and negative voltage inputs. The input multiplexers of the ADC can connect these inputs to one of several internal nodes (e.g., temperature sensor) or to external signals via analog ports (APORT0, APORT1, APORT2, APORT3 or APORT4).
Page 853 Reference Manual ADC - Analog to Digital Converter Multiple peripherals may request the same shared system bus (BUSAX, BUSAY, BUSBX, etc.). When this happens, a conflict status is generated and that bus is kept floating. If this happens with the ADC, the PROGERR field in ADCn_STATUS is set to BUSCONF, and an interrupt may be generated (if enabled).
Page 854 Reference Manual ADC - Analog to Digital Converter 26.3.7.2 Configuring ADC Inputs in Scan Mode In scan mode, the ADC can sample and convert up to 32 external channels on each conversion trigger. Internal channels are not avail- able in scan mode. The ADC's scanner logic automatically changes the input mux settings between conversions, eliminating the need for firmware intervention.
Page 855 Reference Manual ADC - Analog to Digital Converter SCANINPUTSEL APORT1CH16TO23 APORT1CH16TO23 APORT4CH8TO15 APORT1CH16TO23 APORT-Channel (Positive) APORT-Channel (Negative) I/O Differential SCANMASK SCANINPUTID Figure 26.7. ADC Differential Scan Mode Example In certain applications it may be desirable to perform differential conversions on several channels against a common voltage. The ADCn_SCANNEGSEL register allows eight of the SCANINPUTIDs to re-map the negative terminal of a differential conversion to a common channel.
Page 856: Reference Selection And Input Range Definition
Reference Manual ADC - Analog to Digital Converter 26.3.7.3 APORT Conflicts The ADC shares common analog buses connected to its APORTs (1-4) with other analog peripherals (see device-specific data sheet). As the ADC performs single or scan conversions, it requests the shared buses and sends selections for the control switches to connect the desired I/O pins.
Page 857 Reference Manual ADC - Analog to Digital Converter 26.3.8.1 Basic Full-Scale Voltage Configuration Basic configuration of the VFS (full scale voltage) for the converter is done by programming the REF bitfield in ADCn_SINGLECTRL (for single channel mode) or ADCn_SCANCTRL (for scan mode) to any of the pre-defined options. The list of available pre-defined VFS options is: •...
Page 858 Reference Manual ADC - Analog to Digital Converter 26.3.8.2 Advanced Full-Scale Voltage Configuration For most applications, the pre-defined VFS options described in 26.3.8.1 Basic Full-Scale Voltage Configuration are suitable. Advanced VFS configurations are also possible by programming the REF bitfield in ADCn_SINGLECTRL or ADCn_SCANCTRL to the CONF op- tion.
Page 859 Reference Manual ADC - Analog to Digital Converter The maximum and minimum input voltage which the ADC can recognize at any external pin is limited to the minimum of the V IOVDD supply voltages (where V is VDDX_ANA, as described in 26.3.5 Power Supply).
Page 860: Programming Of Bias Current
Reference Manual ADC - Analog to Digital Converter 26.3.9 Programming of Bias Current The ADC uses a chip-level bias generator to provide bias current for its operation. The ADC's internal bias can be scaled by ADCBIA- SPROG field of the ADCn_BIASPROG register. At lower conversion speeds, the ADCBIASPROG can be used to lower active power. Some commonly used settings are given in the ADCBIASPROG register description.
Page 861 Reference Manual ADC - Analog to Digital Converter 26.3.10.2 Repetitive Mode Both single channel and scan mode can be run as a one shot conversion or in repetitive mode. The REP bitfield in ADCn_SIN- GLECTRL/ADCn_SCANCTRL registers can be used to activate the repetitive mode for single and scan respectively. In order to achieve the maximum sampling rate of 1 Msps, repetitive mode should be used.
Page 862 Reference Manual ADC - Analog to Digital Converter 26.3.10.3 Conversion Trigger The conversion modes can be activated by writing a 1 to the SINGLESTART or SCANSTART bit in the ADCn_CMD register. The con- versions can be stopped by writing a 1 to the SINGLESTOP or SCANSTOP bit in the ADCn_CMD register. A START command will have priority over a STOP command.
Page 863 Reference Manual ADC - Analog to Digital Converter running, then the CMU automatically turns it on when the ADC sends a clock request. In such a case, it takes (7 ADC_CLK cycles + the oscillator startup time) for the ADC_CLK to start. The oscillator startup time can be found in the device data sheet. When triggering repeat mode using PRS and then stopping the triggered mode using STOP command, ensure that the PRS pulse used to generate the repeat mode has gone low by the time the STOP command is issued.
Page 864 Reference Manual ADC - Analog to Digital Converter 26.3.10.4 Output Results ADC output results are presented in 2’s complement form and the format for single ended and differential conversions are given in Table 26.2 ADC Single Ended Conversion on page 864 Table 26.3 ADC Differential Conversion on page 864, respectively.
Page 865 Reference Manual ADC - Analog to Digital Converter 26.3.10.6 Oversampling To achieve higher accuracy, hardware oversampling can be enabled individually for each mode (Set RES in ADCn_SINGLECTRL/ ADCn_SCANCTRL to 0x3). The oversampling rate (OVSRSEL in ADCn_CTRL) can be set to any integer power of 2 from 2 to 4096 and the configuration is shared between the scan and single channel mode (OVSRSEL field in ADCn_CTRL).
Page 866 Reference Manual ADC - Analog to Digital Converter 26.3.10.8 Channel Connection The inputs are connected to the analog ADC at the beginning of the acquisition phase and are disconnected at the end of the acquisi- tion phase. The time when the APORT switches are closed (for the next input to be converted) can be controlled by the CHCONMODE bitfield in the ADCn_CTRL register.
Page 867: Interrupts, Prs Output
Reference Manual ADC - Analog to Digital Converter 26.3.11 Interrupts, PRS Output The single and scan modes have separate SINGLE and SCAN interrupt flags indicating whether corresponding FIFO contains DVL # of valid conversion data. Corresponding interrupt enable bit has to be set in ADCn_IEN in order to generate interrupts. For these inter- rupts, there is no software clear mechanism by writing to ADCn_IFC.
Page 868: Em2 Deep Sleep Or Em3 Stop Operation
Reference Manual ADC - Analog to Digital Converter 26.3.13.2 Gain Calibration Offset calibration must be performed prior to gain calibration. The Gain Calibration is done in the following manner: 1. Select an external ADC channel for single channel conversion (a differential channel can also be used). 2.
Page 869: Async Adc_Clk Usage Restrictions And Benefits
Reference Manual ADC - Analog to Digital Converter 26.3.15 ASYNC ADC_CLK Usage Restrictions and Benefits When the ADC_CLK is chosen to come from ASYNCCLK, (ADCCLKMODE is set to ASYNC), the ADC_CLK and the ADC peripheral clock are considered asynchronous and this adds some restrictions: •...
Page 870: Adc Programming Model
Reference Manual ADC - Analog to Digital Converter 26.3.17 ADC Programming Model The ADC configuration registers are considered static and can only be updated when (1) ADC is in SYNC mode and (2) ADC is idle. ADC is considered busy when it is doing conversions (either the SINGLEACT or SCANACT status flag is high) or when it is warmed up (one of the following status flags is high: WARM, SINGLEREFWARM, SCANREFWARM).
Page 871: Register Map
Reference Manual ADC - Analog to Digital Converter 26.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ADCn_CTRL Control Register 0x008 ADCn_CMD Command Register 0x00C ADCn_STATUS Status Register 0x010 ADCn_SINGLECTRL Single Channel Control Register 0x014 ADCn_SINGLECTRLX...
Page 872: Register Description
Reference Manual ADC - Analog to Digital Converter 26.5 Register Description 26.5.1 ADCn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:30 CHCONREFWARMI- Channel Connect and Reference Warm Sel When ADC is IDLE Channel connect and reference warm preference Value Mode Description...
Page 873 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Value Mode Description 2 samples for each conversion result 4 samples for each conversion result 8 samples for each conversion result 16 samples for each conversion result 32 samples for each conversion result 64 samples for each conversion result X128 128 samples for each conversion result...
Page 874 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description ASYNCCLKEN Selects ASYNC CLK Enable Mode When ADCCLKMODE=1 Write a 1 to keep ASYNC CLK always enabled. Value Mode Description ASNEEDED ASYNC CLK is enabled only during ADC Conversion. ALWAYSON ASYNC CLK is always enabled.
Page 875: Adcn_Cmd - Command Register
Reference Manual ADC - Analog to Digital Converter 26.5.2 ADCn_CMD - Command Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCANSTOP...
Page 876: Adcn_Status - Status Register
Reference Manual ADC - Analog to Digital Converter 26.5.3 ADCn_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCANDV...
Page 877 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SINGLEACT Single Channel Conversion Active Single channel conversion is active or has pending conversions. silabs.com | Building a more connected world. Rev. 1.1 | 877...
Page 878: Adcn_Singlectrl - Single Channel Control Register
Reference Manual ADC - Analog to Digital Converter 26.5.4 ADCn_SINGLECTRL - Single Channel Control Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description CMPEN Compare Logic Enable for Single Channel Enable/disable Compare Logic Value Description Disable Compare Logic. Enable Compare Logic.
Page 879 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 23:16 NEGSEL 0xFF Single Channel Negative Input Selection Selects the negative input to the ADC for Single Channel Differential mode (in case of singled ended mode, the negative input is grounded).
Page 880 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description ..APORT0XCH15 Select APORT0XCH15 APORT0YCH0 Select APORT0YCH0 APORT0YCH1 Select APORT0YCH1 APORT0YCH15 Select APORT0YCH15 APORT1XCH0 Select APORT1XCH0 APORT1YCH1 Select APORT1YCH1 ..APORT1YCH31 Select APORT1YCH31 APORT2YCH0 Select APORT2YCH0 APORT2XCH1 Select APORT2XCH1 ..
Page 881 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SUBLSB SUBLSB measurement enabled. OPA3 OPA3 output. Not Applicable if no OPA is available. Single Channel Reference Selection Select reference to ADC single channel mode. Value Mode Description 1V25 VFS = 1.25V with internal VBGR reference VFS = 2.5V with internal VBGR reference...
Page 882 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description ADC will perform one conversion per trigger in single channel mode. ADC will repeat conversions in single channel mode continuously until SINGLESTOP is written. silabs.com | Building a more connected world. Rev.
Page 883: Adcn_Singlectrlx - Single Channel Control Register Continued
Reference Manual ADC - Analog to Digital Converter 26.5.5 ADCn_SINGLECTRLX - Single Channel Control Register Continued Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:29 REPDELAY REPDELAY Select for SINGLE REP Mode Delay value between two repeated conversions. Value Mode Description...
Page 884 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 20:17 PRSSEL Single Channel PRS Trigger Select Select PRS trigger for single channel. Value Mode Description...
Page 885 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 11:8 VINATT Code for VIN Attenuation Factor Used to set the VIN attenuation factor. VREFATT Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5 Used to set VREF attenuation factor. VREFATTFIX Enable Fixed Scaling on VREF Enables fixed scaling on VREF...
Page 886: Adcn_Scanctrl - Scan Control Register
Reference Manual ADC - Analog to Digital Converter 26.5.6 ADCn_SCANCTRL - Scan Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description CMPEN Compare Logic Enable for Scan Enable/disable Compare Logic Value Description Disable Compare Logic. Enable Compare Logic. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 887 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 23:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions Scan Sequence Reference Selection Select reference to ADC scan sequence. Value Mode Description...
Page 888 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Scan conversion mode repeats continuously until SCANSTOP is writ- ten. silabs.com | Building a more connected world. Rev. 1.1 | 888...
Page 889: Adcn_Scanctrlx - Scan Control Register Continued
Reference Manual ADC - Analog to Digital Converter 26.5.7 ADCn_SCANCTRLX - Scan Control Register Continued Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:29 REPDELAY REPDELAY Select for SCAN REP Mode Delay value between two repeated conversions. Value Mode Description...
Page 890 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 20:17 PRSSEL Scan Sequence PRS Trigger Select Select PRS trigger for scan sequence. Value Mode Description...
Page 891 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description 11:8 VINATT Code for VIN Attenuation Factor Used to set the VIN attenuation factor. VREFATT Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5 Used to set VREF attenuation factor. VREFATTFIX Enable Fixed Scaling on VREF Enables fixed scaling on VREF...
Page 892: Adcn_Scanmask - Scan Sequence Input Mask Register
Reference Manual ADC - Analog to Digital Converter 26.5.8 ADCn_SCANMASK - Scan Sequence Input Mask Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:0 SCANINPUTEN 0x00000000 Scan Sequence Input Mask Set one or more bits in this mask to select which inputs are included in scan sequence in either single ended or differential mode.
Page 893 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description INPUT1INPUT2 xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT1 Negative input: ADCn_INPUT2) inclu- xxxxxxxxx1x ded in mask INPUT2INPUT2NEG- xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT2 Negative input: chosen by IN- xxxxxxxx1xx PUT2NEGSEL) included in mask INPUT3INPUT4 xxxxxxxxxxxxxxxxxxxxx (Positive input: ADCn_INPUT3 Negative input: ADCn_INPUT4) inclu-...
Page 894: Adcn_Scaninputsel - Input Selection Register For Scan Mode
Reference Manual ADC - Analog to Digital Converter 26.5.9 ADCn_SCANINPUTSEL - Input Selection Register for Scan Mode Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 28:24...
Page 895 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT1CH8TO15 Select APORT1's CH8-CH15 as ADCn_INPUT16-ADCn_INPUT23 APORT1CH16TO23 Select APORT1's CH16-CH23 as ADCn_INPUT16-ADCn_INPUT23 APORT1CH24TO31 Select APORT1's CH24-CH31 as ADCn_INPUT16-ADCn_INPUT23 APORT2CH0TO7 Select APORT2's CH0-CH7 as ADCn_INPUT16-ADCn_INPUT23 ..APORT3CH0TO7 Select APORT3's CH0-CH7 as ADCn_INPUT16-ADCn_INPUT23 ..
Page 896 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT1CH24TO31 Select APORT1's CH24-CH31 as ADCn_INPUT0-ADCn_INPUT7 APORT2CH0TO7 Select APORT2's CH0-CH7 as ADCn_INPUT0-ADCn_INPUT7 ..APORT3CH0TO7 Select APORT3's CH0-CH7 as ADCn_INPUT0-ADCn_INPUT7 ..APORT4CH0TO7 Select APORT4's CH0-CH7 as ADCn_INPUT0-ADCn_INPUT7 ..silabs.com | Building a more connected world. Rev.
Page 897: Adcn_Scannegsel - Negative Input Select Register For Scan
Reference Manual ADC - Analog to Digital Converter 26.5.10 ADCn_SCANNEGSEL - Negative Input Select Register for Scan Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 15:14...
Page 898 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description INPUT9NEGSEL Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode Selects negative channel Value Mode Description INPUT8 Selects ADCn_INPUT8 as negative channel input INPUT10 Selects ADCn_INPUT10 as negative channel input INPUT12 Selects ADCn_INPUT12 as negative channel input INPUT14...
Page 899: Adcn_Cmpthr - Compare Threshold Register
Reference Manual ADC - Analog to Digital Converter Name Reset Access Description INPUT1 Selects ADCn_INPUT1 as negative channel input INPUT3 Selects ADCn_INPUT3 as negative channel input INPUT5 Selects ADCn_INPUT5 as negative channel input INPUT7 Selects ADCn_INPUT7 as negative channel input 26.5.11 ADCn_CMPTHR - Compare Threshold Register Offset Bit Position...
Page 900: Eration
Reference Manual ADC - Analog to Digital Converter 26.5.12 ADCn_BIASPROG - Bias Programming Register for Various Analog Blocks Used in ADC Operation Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions GPBIASACC...
Page 901: Adcn_Cal - Calibration Register
Reference Manual ADC - Analog to Digital Converter 26.5.13 ADCn_CAL - Calibration Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description CALEN Calibration Mode is Enabled When enabled, the adc performs conversion and sends raw data to the ADC fifos. This can also be used to debug the adc data conversion 30:24 SCANGAIN...
Page 902 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SINGLEOFFSET Single Mode Offset Calibration Value for Differential or Positive Single-ended Mode This register contains the offset calibration value used with single conversions for differential or positive single-ended mode. This field is set to the production offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device.
Page 903: Adcn_If - Interrupt Flag Register
Reference Manual ADC - Analog to Digital Converter 26.5.14 ADCn_IF - Interrupt Flag Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM23ERR...
Page 904 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SCANOF Scan FIFO Overflow Interrupt Flag Indicates scan result FIFO overflow when this bit is set. An overflow occurs if there is not room in the FIFO to store a new result.
Page 905: Adcn_Ifs - Interrupt Flag Set Register
Reference Manual ADC - Analog to Digital Converter 26.5.15 ADCn_IFS - Interrupt Flag Set Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM23ERR...
Page 906 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SINGLEOF Set SINGLEOF Interrupt Flag Write 1 to set the SINGLEOF interrupt flag Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions silabs.com | Building a more connected world.
Page 907: Adcn_Ifc - Interrupt Flag Clear Register
Reference Manual ADC - Analog to Digital Converter 26.5.16 ADCn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM23ERR...
Page 908 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SCANUF (R)W1 Clear SCANUF Interrupt Flag Write 1 to clear the SCANUF interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). SINGLEUF (R)W1 Clear SINGLEUF Interrupt Flag...
Page 909: Adcn_Ien - Interrupt Enable Register
Reference Manual ADC - Analog to Digital Converter 26.5.17 ADCn_IEN - Interrupt Enable Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM23ERR...
Page 910: Adcn_Singledata - Single Conversion Result Data (Actionable Reads)
Reference Manual ADC - Analog to Digital Converter Name Reset Access Description SINGLEOF SINGLEOF Interrupt Enable Enable/disable the SINGLEOF interrupt Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SCAN SCAN Interrupt Enable Enable/disable the SCAN interrupt SINGLE SINGLE Interrupt Enable...
Page 911: Adcn_Singledatap - Single Conversion Result Data Peek Register
Reference Manual ADC - Analog to Digital Converter 26.5.20 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:0 DATAP 0x00000000 Single Conversion Result Data Peek The register holds the results from the last single channel mode conversion. Reading this field will not pop an entry from the SINGLE FIFO.
Page 912: Adcn_Scandataxp - Scan Sequence Result Data + Data Source Peek Register
Reference Manual ADC - Analog to Digital Converter 26.5.22 ADCn_SCANDATAX - Scan Sequence Result Data + Data Source Register (Actionable Reads) Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 20:16...
Page 913: Adcn_Aportreq - Aport Request Status Register
Reference Manual ADC - Analog to Digital Converter 26.5.24 ADCn_APORTREQ - APORT Request Status Register Offset Bit Position 0x07C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YREQ...
Page 914: Adcn_Aportconflict - Aport Conflict Status Register
Reference Manual ADC - Analog to Digital Converter 26.5.25 ADCn_APORTCONFLICT - APORT Conflict Status Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YCONFLICT 0...
Page 915: Adcn_Singlefifocount - Single Fifo Count Register
Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT0XCONFLICT 0 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral Reports if the bus connected to APORT0X is is also being requested by another peripheral 26.5.26 ADCn_SINGLEFIFOCOUNT - Single FIFO Count Register Offset Bit Position...
Page 916: Adcn_Singlefifoclear - Single Fifo Clear Register
Reference Manual ADC - Analog to Digital Converter 26.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register Offset Bit Position 0x08C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions SINGLEFIFOCLEAR...
Page 917: Adcn_Aportmasterdis - Aport Bus Master Disable Register
Reference Manual ADC - Analog to Digital Converter 26.5.30 ADCn_APORTMASTERDIS - APORT Bus Master Disable Register Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT4YMASTER-...
Page 918 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT3XMASTER- APORT3X Master Disable Determines if the ADC will request this APORT bus (if selected by POSSEL or NEGSEL or SCANINPUTSEL). When 1, ADC only passively monitors the APORT bus and the selection of the channel for the selected bus is ignored. The channel selection is done by the device that masters the APORT bus.
Page 919 Reference Manual ADC - Analog to Digital Converter Name Reset Access Description APORT mastering enabled APORT mastering disabled Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions silabs.com | Building a more connected world. Rev.
Page 920: Idac - Current Digital To Analog Converter
Reference Manual IDAC - Current Digital to Analog Converter 27. IDAC - Current Digital to Analog Converter Quick Facts What? The IDAC can sink or source a configurable con- stant current. Why? The IDAC can be used to bias external circuits or (in conjunction with the ADC) measure capacitance by IDAC injecting a controlled current into a component.
Page 921: Functional Description
Reference Manual IDAC - Current Digital to Analog Converter 27.3 Functional Description An overview of the IDAC module is shown in Figure 27.1 IDAC Overview on page 921. The IDAC is designed to source or sink a programmable current which can be controlled by setting the range and the step in the RANGESEL and STEPSEL bitfields in IDAC_CURRPROG register.
Page 922: Output Control
Reference Manual IDAC - Current Digital to Analog Converter 27.3.3 Output Control The IDAC output enable is controlled separately for APORT and main pad. If APORTOUTENPRS/MAINOUTENPRS is set, output ena- ble is controlled by PRS, else it is controlled by software via APORTOUTEN/MAINOUTEN. 27.3.4 APORT Configuration The IDAC APORT outputs can be routed to pins through the APORT system.
Page 923: Prs Triggered Charge Injection
Reference Manual IDAC - Current Digital to Analog Converter 27.3.9 PRS Triggered Charge Injection The amount of charge sourced or sunk by the IDAC can be controlled by the PRS (e.g., using a timer as producer) via the output switch. Figure 27.2 IDAC Charge Injection Example on page 923 shows a case where the IDAC is configured to periodically supply charge using the PRS.
Page 924: Register Description
Reference Manual IDAC - Current Digital to Analog Converter 27.5 Register Description 27.5.1 IDAC_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 23:20...
Page 925 Reference Manual IDAC - Current Digital to Analog Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTOUTENPRS PRS Controlled APORT Output Enable Enable PRS Control of the IDAC APORT output enable. Value Description APORT output enable controlled by IDAC_APORTOUTEN.
Page 926: Idac_Curprog - Current Programming Register
Reference Manual IDAC - Current Digital to Analog Converter Name Reset Access Description APORTOUTEN APORT Output Enable Set to enable the IDAC output to APORT if APORTOUTENPRS is not set. MINOUTTRANS Minimum Output Transition Enable Set to enable minimum output transition mode for the IDAC. CURSINK Current Sink Enable Set to enable the IDAC as a current sink.
Page 927: Idac_Dutyconfig - Duty Cycle Configuration Register
Reference Manual IDAC - Current Digital to Analog Converter 27.5.3 IDAC_DUTYCONFIG - Duty Cycle Configuration Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions EM2DUTYCYCLE-...
Page 928: Idac_If - Interrupt Flag Register
Reference Manual IDAC - Current Digital to Analog Converter 27.5.5 IDAC_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT...
Page 929: Idac_Ifc - Interrupt Flag Clear Register
Reference Manual IDAC - Current Digital to Analog Converter 27.5.7 IDAC_IFC - Interrupt Flag Clear Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORTCONFLICT...
Page 930: Idac_Aportreq - Aport Request Status Register
Reference Manual IDAC - Current Digital to Analog Converter 27.5.9 IDAC_APORTREQ - APORT Request Status Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions APORT1YREQ...
Page 931: Lesense - Low Energy Sensor Interface
Reference Manual LESENSE - Low Energy Sensor Interface 28. LESENSE - Low Energy Sensor Interface Quick Facts What? LESENSE is a low energy sensor interface capable of autonomously collecting and processing data from multiple sensors even when in EM2. Flexible config- uration makes LESENSE a versatile sensor inter- face compatible with a wide range of sensors and measurement schemes.
Page 932: Features
Reference Manual LESENSE - Low Energy Sensor Interface 28.2 Features • Up to 16 sensors • Autonomous sensor monitoring in EM0, EM1, and EM2 • Highly configurable decoding of sensor results • Interrupt on sensor events • Configurable enable signals to external sensors •...
Page 933: Channel Configuration
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.1 Channel Configuration LESENSE has 16 individually configurable channels, each with its own set of configuration registers. Channel configuration is split into three registers; CHx_TIMING, CHx_INTERACT, and CHx_EVAL. Individual timing for each sensor is configured in CHx_TIMING, sen- sor interaction is configured in CHx_INTERACT, and configurations regarding evaluation of the measurements are done in CHx_EVAL.
Page 934: Scan Sequence
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.2 Scan Sequence LESENSE runs on LFACLK , which is a prescaled version of LFACLK. The prescaling factor for LFACLK is selected in LESENSE LESENSE the CMU, available prescaling factors are: • DIV1: LFACLK = LFACLK/1 LESENSE •...
Page 935: Sensor Timing
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.3 Sensor Timing For each channel in the scan sequence, the LESENSE interface goes through three phases: idle, excite, and measure. The durations of the excite and measure phases are configured in the CHx_TIMING registers. The excite phase duration can be configured to be either a number of AUXHFRCO cycles or a number of LFACLK cycles, depending on which one is selected by the EXCLK bit in LESENSE...
Page 936 Reference Manual LESENSE - Low Energy Sensor Interface INIT START SAMPLE SAMPLEDLY STARTDLY MEASUREDLY LFACLK LESENSE EXTIME EXCITE AUXHFRCO Idle phase Excite phase Measure phase Idle phase Figure 28.5. Timing Diagram, LFACLK Based Timing silabs.com | Building a more connected world. Rev.
Page 937: Sensor Interaction
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.4 Sensor Interaction Many sensor types require some type of excitation in order to work. The LESENSE module can generate a variety of sensor stimuli, both on the same pin as the measurement is to be made on, as well as alternative pins. By default, excitation is performed on the pin associated with the channel (i.e., excitation and sensor measurement is performed on the same pin).
Page 938: Sensor Sampling
Reference Manual LESENSE - Low Energy Sensor Interface LFACLK LESENSE EXCITE Idle phase Excite phase Measure phase Idle phase Channel pin IDLECONF EXMODE IDLECONF ALTEX=0 Alternate excite pin IDLECONF Channel pin IDLECONF IDLECONF ALTEX=1 Alternate excite pin IDLECONF EXMODE IDLECONF Figure 28.6.
Page 939: Sensor Evaluation
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.6 Sensor Evaluation When a measurement phase is completed, the sensor data is evaluated by the evaluation block. If the sensor data is taken from ACMP sample in a single point in time (CHx_INTERACT_SAMPLE = ACMP), the evaluation is limited to determining if the sensor data is 0 or 1.
Page 940 Reference Manual LESENSE - Low Energy Sensor Interface 28.3.6.2 Sliding Window In sliding window mode, the sensor data is compared against the upper and lower limits of a window range. The window is defined by a base, given by CHx_EVAL_COMPTHRES, and a size configured in EVALCTRL_WINSIZE. The window size is constant and the same for all LESENSE channels, while the base is specific to each channel and will be updated by LESENSE when the sensor data is outside the current window range.
Page 941: Decoder
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.7 Decoder Many applications, such as quadrature decoding, require some sort of processing of the sensor readings. In quadrature decoding, the sensors repeatedly pass through a set of states which correspond to the position of the sensors. This sequence, and many other de- coding schemes, can be described as a finite state machine.
Page 942 Reference Manual LESENSE - Low Energy Sensor Interface STATE TCONF Generate PRS SENSORSTATE & ~MASK signals and set COMP & ~MASK interrupt flag NEXTSTATE Generate PRS SENSORSTATE & ~MASK signals and set COMP & ~MASK interrupt flag NEXTSTATE CHAIN _TCONF SENSORSTATE changed &&...
Page 943 Reference Manual LESENSE - Low Energy Sensor Interface PRS_DECCMP = (DECSTATE & ~DECCMPMASK) == (DECCMPVAL & ~DECCMPMASK) Figure 28.12. DECCMP PRS Output To prevent unnecessary interrupt requests or PRS outputs when the decoder toggles back and forth between two states, a hysteresis option is available.
Page 944: Measurement Results
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.8 Measurement Results Part of the LESENSE RAM is treated as a circular buffer for storage of up to 16 sensor measurements results. Each time LESENSE writes data to the result buffer, the result write pointer (PTR_WR) is incremented. Each time a new result is read through the BUFDATA register, the result read pointer (PTR_RD) is incremented.
Page 945: Vdac Interface
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.9 VDAC Interface LESENSE is able to drive the VDAC for generation of accurate reference voltages. This is enabled by setting DACCHxEN in PERCTRL. The refresh rate of the VDAC channels can be configured in DACCONVTRIG in PERCTRL. If DACCONVTRIG is set to CHANNELSTART, the VDAC channels are refreshed prior to each sensor measurement, as depicted in Figure 28.4 Timing Diagram, AUXHFRCO Based Timing on page...
Page 946: Adc Interface
Reference Manual LESENSE - Low Energy Sensor Interface 28.3.12 ADC Interface The LESENSE module can be configured to trigger conversions on ADC0 and use data from ADC0 to evaluate sensor status. In order to do this, the scan mode of the ADC has to be configured. When the sample delay configured in CHx_TIMING_SAMPLEDLY has expired, LESENSE will initiate an ADC sample.
Page 947 Reference Manual LESENSE - Low Energy Sensor Interface 28.3.16.1 Capacitive Sense Figure 28.15 Capacitive Sense Setup on page 947 illustrates how the EFR32 can be configured to monitor four capacitive buttons. ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 Figure 28.15. Capacitive Sense Setup The following steps show how to configure LESENSE to scan through the four buttons 100 times per second, issuing an interrupt if one of them is pressed.
Page 948 Reference Manual LESENSE - Low Energy Sensor Interface 28.3.16.2 LC Sensor Figure 28.16 LC Sensor Setup on page 948 below illustrates how the EFR32 can be set up to monitor four LC sensors. DAC0_OUT0 ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 Figure 28.16. LC Sensor Setup LESENSE can be used to excite and measure the damping factor in LC sensor oscillations.
Page 949 Reference Manual LESENSE - Low Energy Sensor Interface 3. Enable channels 0 through 3 in CHEN. Set IDLECONF for the active channels to DACOUT. The channel pins should be connected to the VDAC output (effectively shorting the LC sensor) in the idle phase to damp the oscillations. 4.
Page 950 Reference Manual LESENSE - Low Energy Sensor Interface 28.3.16.3 LESENSE Decoder 1 The example below illustrates how the LESENSE module can be used for decoding using three sensors Sensor value State Index 010 110 000 100 Figure 28.18. FSM Example 1 Figure 28.18 FSM Example 1 on page 950, configure the following LESENSE registers: 1.
Page 951 Reference Manual LESENSE - Low Energy Sensor Interface 28.3.16.4 LESENSE Decoder 2 The example below illustrates how the LESENSE decoder can be used to implement the state machine seen in Figure 28.19 FSM Ex- ample 2 on page 951. 1XXX 1XXX 0010 0001...
Page 952: Register Map
Reference Manual LESENSE - Low Energy Sensor Interface 28.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LESENSE_CTRL Control Register 0x004 LESENSE_TIMCTRL Timing Control Register 0x008 LESENSE_PERCTRL Peripheral Control Register 0x00C LESENSE_DECCTRL Decoder Control Register...
Page 953 Reference Manual LESENSE - Low Energy Sensor Interface Offset Name Type Description 0x248 LESENSE_CH0_EVAL Scan Configuration LESENSE_CHx_TIMING Scan Configuration LESENSE_CHx_INTERACT Scan Configuration LESENSE_CHx_EVAL Scan Configuration 0x330 LESENSE_CH15_TIMING Scan Configuration 0x334 LESENSE_CH15_INTERACT Scan Configuration 0x338 LESENSE_CH15_EVAL Scan Configuration silabs.com | Building a more connected world. Rev.
Page 954: Register Description
Reference Manual LESENSE - Low Energy Sensor Interface 28.5 Register Description 28.5.1 LESENSE_CTRL - Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x000 Reset Access Name Name Reset Access...
Page 955 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description BUFOW Result Buffer Overwrite If set, LESENSE will always write to the result buffer, even if it is full 15:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions DUALSAMPLE...
Page 956 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10 PRS Channel 10 selected as input PRSCH11 PRS Channel 11 selected as input SCANMODE Configure Scan Mode These bits control how the scan frequency is decided...
Page 957: Lesense_Timctrl - Timing Control Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:29...
Page 958 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description DIV64 The period counter clock frequency is LFACLK LESENSE DIV128 The period counter clock frequency is LFACLK /128 LESENSE Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions LFPRESC...
Page 959: Lesense_Perctrl - Peripheral Control Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:30...
Page 960 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description 21:20 ACMP0MODE ACMP0 Mode Configure how LESENSE controls ACMP0 Value Mode Description DISABLE LESENSE does not control ACMP0 LESENSE controls the input mux (POSSEL) of ACMP0 MUXTHRES LESENSE controls the input mux (POSSEL) and the threshold value (VDDLEVEL) of ACMP0 19:9 Reserved...
Page 961 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description DACCH1EN VDAC CH1 Enable Enable LESENSE control of VDAC0 CH1 DACCH0EN VDAC CH0 Enable Enable LESENSE control of VDAC0 CH0 silabs.com | Building a more connected world. Rev. 1.1 | 961...
Page 962: Lesense_Decctrl - Decoder Control Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.4 LESENSE_DECCTRL - Decoder Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:29...
Page 963 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description PRSCH5 PRS Channel 5 selected as input PRSCH6 PRS Channel 6 selected as input PRSCH7 PRS Channel 7 selected as input PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10...
Page 964 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description PRSCH8 PRS Channel 8 selected as input PRSCH9 PRS Channel 9 selected as input PRSCH10 PRS Channel 10 selected as input PRSCH11 PRS Channel 11 selected as input Reserved To ensure compatibility with future devices, always write bits to 0.
Page 965: Lesense_Biasctrl - Bias Control Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:2...
Page 966: Lesense_Prsctrl - Prs Control Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.7 LESENSE_PRSCTRL - PRS Control Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:17...
Page 967: Lesense_Cmd - Command Register
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.8 LESENSE_CMD - Command Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CLEARBUF...
Page 968: Lesense_Scanres - Scan Result Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.10 LESENSE_SCANRES - Scan Result Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16...
Page 969: Lesense_Status - Status Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.11 LESENSE_STATUS - Status Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:6 Reserved...
Page 970: Lesense_Ptr - Result Buffer Pointers (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.12 LESENSE_PTR - Result Buffer Pointers (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:8...
Page 971: Lesense_Curch - Current Channel Index (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.14 LESENSE_CURCH - Current Channel Index (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:4...
Page 972: Lesense_Sensorstate - Decoder Input Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.16 LESENSE_SENSORSTATE - Decoder Input Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:4...
Page 973: Lesense_Idleconf - Gpio Idle Phase Configuration (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.17 LESENSE_IDLECONF - GPIO Idle Phase Configuration (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x040 Reset Access Name Name Reset Access Description...
Page 974 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description DISABLE CH12 output is disabled in idle phase HIGH CH12 output is high in idle phase CH12 output is low in idle phase CH12 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 4, 5, 7, 10, 12, 13 23:22 CH11...
Page 975 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description 15:14 Channel 7 Idle Phase Configuration This bitfield determines how the channel is configured during the idle phase Value Mode Description DISABLE CH7 output is disabled in idle phase HIGH CH7 output is high in idle phase CH7 output is low in idle phase...
Page 976 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description HIGH CH3 output is high in idle phase CH3 output is low in idle phase CH3 output is connected to VDAC output in idle phase. Note that this mode is only available on channels 4, 5, 7, 10, 12, 13 Channel 2 Idle Phase Configuration This bitfield determines how the channel is configured during the idle phase...
Page 977: Lesense_Altexconf - Alternative Excite Pin Configuration (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.18 LESENSE_ALTEXCONF - Alternative Excite Pin Configuration (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x044 Reset Access Name Name Reset Access Description...
Page 978 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description Value Mode Description DISABLE ALTEX6 output is disabled in idle phase HIGH ALTEX6 output is high in idle phase ALTEX6 output is low in idle phase 11:10 IDLECONF5 ALTEX5 Idle Phase Configuration This bitfield determines how the alternate excite pin is configured during the idle phase Value...
Page 979 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description IDLECONF0 ALTEX0 Idle Phase Configuration This bitfield determines how the alternate excite pin is configured during the idle phase Value Mode Description DISABLE ALTEX0 output is disabled in idle phase HIGH ALTEX0 output is high in idle phase ALTEX0 output is low in idle phase...
Page 980: Lesense_If - Interrupt Flag Register
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.19 LESENSE_IF - Interrupt Flag Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CNTOF...
Page 981 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description CH9 Interrupt Flag Set when channel 9 triggers CH8 Interrupt Flag Set when channel 8 triggers CH7 Interrupt Flag Set when channel 7 triggers CH6 Interrupt Flag Set when channel 6 triggers CH5 Interrupt Flag Set when channel 5 triggers CH4 Interrupt Flag...
Page 982: Lesense_Ifs - Interrupt Flag Set Register
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.20 LESENSE_IFS - Interrupt Flag Set Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CNTOF...
Page 983 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description CH10 Set CH10 Interrupt Flag Write 1 to set the CH10 interrupt flag Set CH9 Interrupt Flag Write 1 to set the CH9 interrupt flag Set CH8 Interrupt Flag Write 1 to set the CH8 interrupt flag Set CH7 Interrupt Flag Write 1 to set the CH7 interrupt flag...
Page 984: Lesense_Ifc - Interrupt Flag Clear Register
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.21 LESENSE_IFC - Interrupt Flag Clear Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CNTOF...
Page 985 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description CH13 (R)W1 Clear CH13 Interrupt Flag Write 1 to clear the CH13 interrupt flag. Reading returns the value of the IF and clears the corresponding interrupt flags (This feature must be enabled globally in MSC.). CH12 (R)W1 Clear CH12 Interrupt Flag...
Page 986: Lesense_Ien - Interrupt Enable Register
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.22 LESENSE_IEN - Interrupt Enable Register Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions CNTOF...
Page 987: Lesense_Syncbusy - Synchronization Busy Register
Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description CH10 CH10 Interrupt Enable Enable/disable the CH10 interrupt CH9 Interrupt Enable Enable/disable the CH9 interrupt CH8 Interrupt Enable Enable/disable the CH8 interrupt CH7 Interrupt Enable Enable/disable the CH7 interrupt CH6 Interrupt Enable Enable/disable the CH6 interrupt CH5 Interrupt Enable...
Page 988: Lesense_Routepen - I/O Routing Register (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.24 LESENSE_ROUTEPEN - I/O Routing Register (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:24...
Page 989 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description CH10PEN CH10 Pin Enable Set this bit to enable LESENSE CH10 pin CH9PEN CH9 Pin Enable Set this bit to enable LESENSE CH9 pin CH8PEN CH8 Pin Enable Set this bit to enable LESENSE CH8 pin CH7PEN CH7 Pin Enable...
Page 990: Lesense_Stx_Tconfa - State Transition Configuration A (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.25 LESENSE_STx_TCONFA - State Transition Configuration a (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x100 Reset Access Name Name Reset Access Description...
Page 991 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in 1.2 Conven- tions 12:8 NEXTSTATE 0xXX Next State Index Index of next state to be entered if the sensor state equals COMP MASK Sensor Mask Set bit X to exclude sensor X from evaluation.
Page 992: Lesense_Stx_Tconfb - State Transition Configuration B (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.26 LESENSE_STx_TCONFB - State Transition Configuration B (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x104 Reset Access Name Name Reset Access Description...
Page 993: Lesense_Bufx_Data - Scan Results (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description 12:8 NEXTSTATE 0xXX Next State Index Index of next state to be entered if the sensor state equals COMP MASK Sensor Mask Set bit X to exclude sensor X from evaluation. COMP Sensor Compare Value State transition is triggered when sensor state equals COMP...
Page 994: Lesense_Chx_Timing - Scan Configuration (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.28 LESENSE_CHx_TIMING - Scan Configuration (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x240 Reset Access Name Name Reset Access Description 31:24 Reserved...
Page 995: Lesense_Chx_Interact - Scan Configuration (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.29 LESENSE_CHx_INTERACT - Scan Configuration (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x244 Reset Access Name Name Reset Access Description 31:22 Reserved...
Page 996 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description NONE No interrupt is generated LEVEL Set interrupt flag if the sensor triggers. POSEDGE Set interrupt flag on positive edge of the sensor state NEGEDGE Set interrupt flag on negative edge of the sensor state BOTHEDGES Set interrupt flag on both edges of the sensor state 13:12...
Page 997: Lesense_Chx_Eval - Scan Configuration (Async Reg)
Reference Manual LESENSE - Low Energy Sensor Interface 28.5.30 LESENSE_CHx_EVAL - Scan Configuration (Async Reg) For more information about asynchronous registers see 4.3 Access to Low Energy Peripherals (Asynchronous Registers). Offset Bit Position 0x248 Reset Access Name Name Reset Access Description 31:23 Reserved...
Page 998 Reference Manual LESENSE - Low Energy Sensor Interface Name Reset Access Description 15:0 COMPTHRES 0xXXXX Decision Threshold for Sensor Data In threshold comparison mode, this bitfield is used to configure threshold used for comparison. In step detection mode, this bitfield is written by LESENSE, and contains the value from previous sensor measurement. In sliding window mode, this bitfield is written by LESENSE, and contains the window base for the given channel.
Page 999: Gpcrc - General Purpose Cyclic Redundancy Check
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 29. GPCRC - General Purpose Cyclic Redundancy Check Quick Facts What? The GPCRC is an error-detecting module commonly used in digital networks and storage systems to de- tect accidental changes to data. Why? The GPCRC module can detect errors in data, giv- ing a higher system reliability and robustness.
Page 1000: Functional Description
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 29.3 Functional Description An overview of the GPCRC module is shown in Figure 29.1 GPCRC Overview on page 1000. GPCRC Module DATAREV bit reversal DATA byte reversal DATABYTEREV INPUTDATA byte byte-level reorder Hardware CRC reversal...

Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

1 About this Document

2 System Overview

3 System Processor

4 Memory and Bus System

5 Radio Transceiver

6 DBG - Debug Interface

7 MSC - Memory System Controller

8 LDMA - Linked DMA Controller

9 RMU - Reset Management Unit

10 EMU - Energy Management Unit

11 CMU - Clock Management Unit

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