Msc_Writecmd - Write Command Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

7.5.4 MSC_WRITECMD - Write Command Register

Offset
0x00C
Reset
Access
Name
Bit Name
31:13 Reserved
12 CLEARWDATA
Will set WDATAREADY and DMA request. Should only be used when no write is active.
11:9 Reserved
8 ERASEMAIN0
Initiate mass erase of region 0. Before use MSC_MASSLOCK must be unlocked. To completely prevent access from soft-
ware, clear bit 0 in the mass erase lock-word (MLW)
7:6 Reserved
5 ERASEABORT
Writing to this bit will abort an ongoing erase sequence.
4 WRITETRIG
Start write of the first word written to MSC_WDATA, then add 4 to ADDR and write the next word if available within a 30us
timeout. When ADDR is incremented past the page boundary, ADDR is set to the base of the page. If WDOUBLE is set,
two words are required every time, and ADDR is incremented by 8.
3 WRITEONCE
Write the word in MSC_WDATA to ADDR. Flash access is returned to the AHB interface as soon as the write operation
completes. The WREN bit in the MSC_WRITECTRL register must be set in order to use this command. Only a single word
is written, but the internal address is also incremented to allow a direct write of a new word without loading a new address
2 WRITEEND
Write 1 to end write mode when using the WRITETRIG command.
1 ERASEPAGE
Erase any user defined page selected by the MSC_ADDRB register. The WREN bit in the MSC_WRITECTRL register must
be set in order to use this command.
0 LADDRIM
Load the internal write address register ADDR from the MSC_ADDRB register. The internal address register ADDR is incre-
mented automatically by 4 after each word is written. When ADDR is incremented past the page boundary, ADDR is set to
the base of the page.
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 W1 Clear WDATA State
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 W1 Mass Erase Region 0
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 W1 Abort Erase Sequence
0 W1 Word Write Sequence Trigger
0 W1 Word Write-Once Trigger
0 W1 End Write Mode
0 W1 Erase Page
0 W1 Load MSC_ADDRB Into ADDR
Bit Position
Reference Manual
MSC - Memory System Controller
1.2 Conven-
1.2 Conven-
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