Leuartn_Clkdiv - Clock Control Register (Async Reg); Leuartn_Startframe - Start Frame Register (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)

For more information about asynchronous registers see
Offset
0x00C
Reset
Access
Name
Bit Name
31:17 Reserved
16:3 DIV
Specifies the fractional clock divider for the LEUART. Bits [7:3] are the fractional part and bits [16:8] are the integer part.
The total divider is ([16:8] + [7:3]/32). To make the math easier the total divider can also be calculated as '([16:8] + [7:0]/
256) where bits [0:2] will always be 0.
2:0 Reserved

19.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)

For more information about asynchronous registers see
Offset
0x010
Reset
Access
Name
Bit Name
31:9 Reserved
8:0 STARTFRAME
When a frame matching STARTFRAME is detected by the receiver, STARTF interrupt flag is set, and if SFUBRX is set,
RXBLOCK is cleared. The start-frame is be loaded into the RX buffer.
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LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0000 RW Fractional Clock Divider
To ensure compatibility with future devices, always write bits to 0. More information in
tions
4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x000 RW Start Frame
Bit Position
Bit Position
Reference Manual
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