Register Description - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

31.6 Register Description

31.6.1 CRYPTO_CTRL - Control Register
Offset
0x000
Reset
Access
Name
Bit Name
31 COMBDMA0WEREQ 0
When cleared, the DATA0WR and DATA0XORWR operate independently. When set, DATA0XORWR requests are also giv-
en through DATA0WR
30 Reserved
29:28 DMA1RSEL
Specifies which read register is used for DMA1RD DMA requests (see related notes in
Sequence)
Value
0
1
2
3
27:26 Reserved
25:24 DMA1MODE
This field determines how data is read when using DMA
Value
0
1
2
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Reset Access Description
RW Combined Data0 Write DMA Request
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW DATA0 DMA Unaligned Read Register Select
Mode Description
DATA1
DDATA1
QDATA1
QDATA1BIG
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW DMA1 Read Mode
Mode Description
FULL Target register is fully read/written during every DMA transaction
LENLIMIT Length Limited. When the current length, i.e. LENGTHA or LENGTHB
indicates that there are less bytes available than the register size, only
length + 1 bytes + necessary zero padding is read. Zero padding is au-
tomatically added when writing.
FULLBYTE Target register is fully read/written during every DMA transaction. Byte-
wise DMA.
Bit Position
Reference Manual
CRYPTO - Crypto Accelerator
1.2 Conven-
31.4.8 DMA and 31.4.3 Repeated
1.2 Conven-
Rev. 1.1 | 1046