Cmu_Hfbusclken0 - High Frequency Bus Clock Enable Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.5.26 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0

Offset
0x0B0
Reset
Access
Name
Bit Name
31:6 Reserved
5 GPCRC
Set to enable the clock for GPCRC.
4 LDMA
Set to enable the clock for LDMA.
3 PRS
Set to enable the clock for PRS.
2 GPIO
Set to enable the clock for GPIO.
1 CRYPTO0
Set to enable the clock for CRYPTO0.
0 LE
Set to enable the clock for LE. Interface used for bus access to Low Energy peripherals.
silabs.com | Building a more connected world.
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW General Purpose CRC Clock Enable
0 RW Linked Direct Memory Access Controller Clock Enable
0 RW Peripheral Reflex System Clock Enable
0 RW General purpose Input/Output Clock Enable
0 RW Advanced Encryption Standard Accelerator 0 Clock Enable
0 RW Low Energy Peripheral Interface Clock Enable
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
Rev. 1.1 | 344