Emu_Dcdczdetctrl - Dcdc Power Train Nfet Zero Current Detector Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

10.5.17 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register

Offset
0x050
Reset
Access
Name
Bit Name
31:10 Reserved
9:8 ZDETBLANKDLY
Reserved for internal use. Do not change.
7 Reserved
6:4 ZDETILIMSEL
Zero detector is reconfigured as low-side reverse current limiter when LNFORCECCM=1 in LN mode. The configuration of
this register is calculated by the allowed average reverse current I_RMAX through the equation: ZDETILIMSEL=(I_RMAX
+40mA)*1.5/(2.5mA*(NFETCNT+1)), where 40mA represents the current ripple with some margin, and the factor of 1.5 ac-
counts for detecting error and other variations. When the battery can tolerate large reverse current, it is recommended to
have I_RMAX=160mA to maximize ZDETILIMSEL to 7 with NFETCNT=15. Note that when LNFORCECCM=1 but ZDETI-
LIMSEL=0, the DCDC's behavior will be very similar to when LNFORCECCM=0 - that is, the DCDC will be in DCM mode.
When LNFORCECCM=0, the zero detector will only detect zero-crossings (reverse-current limit=0 mA) and this register is
ignored. Reset with POR, Hard Pin Reset, or BOD reset.
3:0 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x1 RW Reserved for internal use. Do not change.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x5 RW Reverse Current Limit Level Selection for Zero Detector
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Bit Position
Reference Manual
EMU - Energy Management Unit
1.2 Conven-
1.2 Conven-
1.2 Conven-
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