Msc_Status - Status Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

7.5.7 MSC_STATUS - Status Register

Offset
0x01C
Reset
Access
Name
Bit Name
31:28 PWRUPCKBDFAIL-
COUNT
This field tells how many times checkboard pattern check fail occured after a reset sequence.
27:24 WDATAVALID
This field tells how many valid data in the write buffer, each bit indicates one buffer entry
23:7 Reserved
6 PCRUNNING
This bit is set while the performance counters are running. When one performance counter reaches the maximum value,
this bit is cleared.
5 ERASEABORTED
When set, the current erase operation was aborted by interrupt.
4 WORDTIMEOUT
When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the
flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands
in MSC_WRITECMD are triggered.
3 WDATAREADY
When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated
with the next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.
2 INVADDR
Set when software attempts to load an invalid (unmapped) address into ADDR
1 LOCKED
When set, the last erase or write is aborted due to erase/write access constraints
0 BUSY
When set, an erase or write operation is in progress and new commands are ignored
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Reset Access Description
0x0 R Flash Power Up Checkerboard Pattern Check Fail Count
0x0 R Write Data Buffer Valid Flag
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 R Performance Counters Running
0 R The Current Flash Erase Operation Aborted
0 R Flash Write Word Timeout
1 R WDATA Write Ready
0 R Invalid Write Address or Erase Page
0 R Access Locked
0 R Erase/Write Busy
Bit Position
Reference Manual
MSC - Memory System Controller
1.2 Conven-
Rev. 1.1 | 140