Usartn_Status - Usart Status Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

18.5.5 USARTn_STATUS - USART Status Register

Offset
0x010
Reset
Access
Name
Bit Name
31:18 Reserved
17:16 TXBUFCNT
Count of TX buffer entry 0, entry 1, and TX shift register. For large frames, the count is only of TX buffer entry 0 and the TX
shifter register.
15 Reserved
14 TIMERRESTARTED
When the timer is restarting itself on each TCMP event, a TIMERRESTARTED value of 0x0 indicates the first TCMP event
in the sequence of multiple TCMP events. Any non TCMP timer start events will clear TIMERRESTARTED. When there is a
TCMP interrupt and TIMERRESTARTED is 0x0, an interrupt service routine can set a TCMP event counter variable in
memory to 0x1 to indicate the first TCMP interrupt of the sequence.
13 TXIDLE
Set when TX idle
12 RXFULLRIGHT
When set, the entire RX buffer contains right data. Only used in I2S mode
11 RXDATAVRIGHT
When set, reading RXDATA or RXDATAX gives right data. Else left data is read. Only used in I2S mode
10 TXBSRIGHT
When set, the TX buffer expects at least a single right data. Else it expects left data. Only used in I2S mode
9 TXBDRIGHT
When set, the TX buffer expects double right data. Else it may expect a single right data or left data. Only used in I2S mode
8 RXFULL
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one
more frame in the receive shift register.
7 RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
6 TXBL
Indicates the level of the transmit buffer. If TXBIL is 0x0, TXBL is set whenever the transmit buffer is completely empty.
Otherwise TXBL is set whenever the TX Buffer becomes half full.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 R TX Buffer Count
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 R The USART Timer Restarted Itself
1 R TX Idle
0 R RX Full of Right Data
0 R RX Data Right
0 R TX Buffer Expects Single Right Data
0 R TX Buffer Expects Double Right Data
0 R RX FIFO Full
0 R RX Data Valid
1 R TX Buffer Level
Bit Position
Reference Manual
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1.2 Conven-
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