11.5.14 CMU_DBGCLKSEL - Debug Trace Clock Select
Offset
0x070
Reset
Access
Name
Bit
Name
31:1
Reserved
0:0
DBG
Select clock used for debug trace.
Value
0
1
11.5.15 CMU_HFCLKSEL - High Frequency Clock Select Command Register
Offset
0x074
Reset
Access
Name
Bit
Name
31:3
Reserved
2:0
HF
Selects the clock source for HFCLK. Note that selecting an oscillator that is disabled will cause the system clock to stop.
Check the status register and confirm that oscillator is ready before switching. If the system can deal with a temporarily
stopped system clock, then it is okay to switch to an oscillator as soon as the status register indicates that the oscillator has
been enabled successfully.
Value
1
2
3
4
5
7
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Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0
RW
Debug Trace Clock
Mode
Description
AUXHFRCO
AUXHFRCO is the debug trace clock
HFCLK
HFCLK is the debug trace clock
Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0
W1
HFCLK Select
Mode
Description
HFRCO
Select HFRCO as HFCLK
HFXO
Select HFXO as HFCLK
LFRCO
Select LFRCO as HFCLK
LFXO
Select LFXO as HFCLK
HFRCODIV2
Select HFRCO divided by 2 as HFCLK
CLKIN0
Select CLKIN0 as HFCLK
Bit Position
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 329
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