Programming Model - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

Reference Manual
SMU - Security Management Unit

12.3.2 Programming Model

The SMU does not provide any access control out of reset and needs to be configured by software. SMU access controls should be
configured along with the MPU configuration. This is typically performed in a bootloader or other low level RTOS kernel/supervisor code
prior to user code or other non-privileged code execution. At least one MPU region will be allocated to the entire peripheral region as a
full access region (0x4000_0000 - 0x4006_FFFF). An RTOS kernel/supervisor can dynamically allocate peripheral accessibility by
maintaining the hardware and software contexts available to each task. In the chart below there are mutiple tasks and the system
switches between Task A and Task B via the RTOS handler. There are 16 peripherals shown in the example split between two regions.
Task A has rights to access peripherals 0, 1, 4, 5 and 7, whereas task B has rights to access the complement of A (2, 3, and 6). After a
Task B IRQ, the privileged OS handler is entered which signals the supervisor to reprogram the regions using the SMU based on an
access control list. Control is then handed to Task B in non-privileged mode.
Figure 12.2. Peripheral Access Control Example
All hardware protections happen immediately in response to SMU configuration register writes without any latency cycles. However,
since software instructions may be optimized or pipelined, it is important to make sure that software memory barrier instructions are
used as needed after any SMU re-configuration before moving on or changing contexts. This ensures that the hardware context switch
has taken full effect.
For the remainder of this section, the programming model is split into general SMU controls and component-specific controls (e.g.,
PPU).
12.3.2.1 Interrupt Control/Status
The SMU follows the standard EFR32 interrupt programming model with SMU_IF/IFS/IFC/IEN registers.
There is one interrupt bit PPUPRIV that will trigger on privilege faults detected by the PPU. Such fault mechanisms are configured as
specified in 12.3.2.2 PPU Control
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