Lesense_Timctrl - Timing Control Register (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

28.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg)

For more information about asynchronous registers see
Offset
0x004
Reset
Access
Name
Bit Name
31:29 Reserved
28 AUXSTARTUP
This bit can be set to ONDEMAND to delay startup of the AUXHFRCO when high frequency timer is used
Value
0
1
27:24 Reserved
23:22 STARTDLY
Delay sensor interaction STARTDELAY LFACLK
21:20 Reserved
19:12 PCTOP
These bits contain the top value for the period counter.
11 Reserved
10:8 PCPRESC
This bitfield is used to divide the clock to the period counter
Value
0
1
2
3
4
5
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4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW AUXHFRCO Startup Configuration
Mode Description
PREDEMAND AUXHFRCO is started half a clock cycle before it's needed
ONDEMAND AUXHFRCO is started at the time it is needed
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Start Delay Configuration
LESENSE
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x00 RW Period Counter Top Value
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Period Counter Prescaling
Mode Description
DIV1 The period counter clock frequency is LFACLK
DIV2 The period counter clock frequency is LFACLK
DIV4 The period counter clock frequency is LFACLK
DIV8 The period counter clock frequency is LFACLK
DIV16 The period counter clock frequency is LFACLK
DIV32 The period counter clock frequency is LFACLK
LESENSE - Low Energy Sensor Interface
Bit Position
cycles for each channel
Reference Manual
Registers).
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
/1
LESENSE
/2
LESENSE
/4
LESENSE
/8
LESENSE
/16
LESENSE
/32
LESENSE
Rev. 1.1 | 957