Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 159

8.3.1.9 DMA Size and Source/Destination Increment Programming
The DMA channels' SIZE, SRCINC, and DSTINC bit-fields are programmed to best utilize memory resources. They provide a means
for memory packing and unpacking, as well as for matching the size of data being transmitted to or received from an IO peripheral. The
following figure shows how 32-bit words of data are read from a memory source into the DMA's internal transfer FIFO, and then written
out to the memory destination. The memory organization in bytes is shown as well as the first read to and write from the DMA's FIFO.
destination
The next example shows four variations of half-word sized transfers, with all possible combinations of half- and full-word source and
destination increments. Note that when the size and source/destination increments are all configured for half-word, the resulting DMA
transfer organization is equivalent to the full-word sized transfer in the previous example. The difference is that the half-word configura-
tion requires twice as many DMA transfers.
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Memory
source
kB3 kB2 kB1
0x200
lB3 lB2 lB1
mB3 mB2 mB1
nB3 nB2 nB1
oB3 oB2 oB1
pB3 pB2 pB1
qB3 qB2 qB1
rB3 rB2 rB1
sB3 sB2 sB1
tB3 tB2 tB1
uB3 uB2 uB1
vB3 vB2 vB1
wB3 wB2 wB1
xB3 xB2 xB1
yB3 yB2 yB1
zB3 zB2 zB1
0x400
kB3 kB2 kB1
lB3 lB2 lB1
mB3 mB2 mB1
Figure 8.3. Memory-to-Memory Transfer WORD Size Example
First read transmit data=
kB0
kB3 kB2
lB0
mB0
Next read data=
nB0
oB3 opB2 oB1
oB0
pB0
qB0
rB0
DMA Controller FIFO
sB0
kB3 kB2
tB0
lB3 lB2
uB0
mB3 mB2
vB0
nB3 nB2
wB0
xB0
yB0
zB0
kB0
lB0
mB0
Next write data=
nB3 nB2 nB1
First write transmit data=
kB3 kB2 kB1
size[1:0] = WORD
src_inc[1:0 ]= WORD
dst_inc[1:0 ]= WORD
Reference Manual
LDMA - Linked DMA Controller
kB1 kB0
oB0
kB1 kB0
lB1 lB0
mB1 mB0
nB1 nB0
nB0
kB0
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