Table of Contents
Advertisement
9.3.2 RMU_RSTCAUSE Register
Whenever a reset source is active, the corresponding bit in the RMU_RSTCAUSE register is set. At startup the program code may
investigate this register in order to determine the cause of the reset. The register is cleared upon POR and software write to
RMU_CMD_RCCLR. The register should be cleared after the value has been read at startup, otherwise the register may indicate multi-
ple causes for the reset at next startup.
RMU_RSTCAUSE should be interpreted according to
9.2 RMU Reset Cause Register Interpretation on page
is invalidated (i.e. can not be trusted) if one of the bits to the right of it does not match the table. X bits are don't care.
Note:
Notice that it is possible to have multiple reset causes. For example, an external reset and a watchdog reset may happen simultaneous-
ly.
RMU_RSTCAUSE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
1
X
1
X
X
1
Pin reset configured as hard/soft
silabs.com | Building a more connected world.
Table 9.2 RMU Reset Cause Register Interpretation on page
202, the reset causes are ordered by severity from right to left. A reset cause bit
Table 9.2. RMU Reset Cause Register Interpretation
X
X
X
X
X
X
X
X
X
X
X
1
X
X
1
X
X
1
X
X
1
1
0
0
0/X
X
1
0
0
0/X
X
1
0
0
0/X
X
1
0
0
0/X
Reset cause
X
1
Power on reset
1
0
Brown-out on AVDD power
X
0
Brown-out on DVDD power
X
0
Brown-out on DEC power
X
0
Pin reset
0
0
Lockup reset
0
0
System reset request
0
0
Watchdog reset
0
0
System has been in EM4
Reference Manual
RMU - Reset Management Unit
202. In
Rev. 1.1 | 202
Table
Advertisement
Table of Contents
Need help?
Do you have a question about the EFR32xG14 Wireless Gecko and is the answer not in the manual?
Questions and answers