Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 564

Bit Name
1
13 RXINV
Setting this bit will invert the input to the USART receiver.
Value
0
1
12 TXBIL
Determines the interrupt and status level of the transmit buffer.
Value
0
1
11 CSMA
This register determines the action to be performed when slave-select is configured as an input and driven low while in
master mode.
Value
0
1
10 MSBF
Decides whether data is sent with the least significant bit first, or the most significant bit first.
Value
0
1
9 CLKPHA
Determines where data is set-up and sampled according to the bus clock when in synchronous mode.
Value
0
1
8 CLKPOL
Determines the clock polarity of the bus clock used in synchronous mode.
Value
0
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset Access Description
Output from the transmitter is inverted before it is passed to U(S)n_TX
0 RW Receiver Input Invert
Description
Input is passed directly to the receiver
Input is inverted before it is passed to the receiver
0 RW TX Buffer Interrupt Level
Mode Description
EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer be-
comes empty. TXBL is cleared when the buffer becomes nonempty.
HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to
half-full or empty. TXBL is cleared when the buffer becomes full.
0 RW Action on Slave-Select in Master Mode
Mode Description
NOACTION No action taken
GOTOSLAVEMODE Go to slave mode
0 RW Most Significant Bit First
Description
Data is sent with the least significant bit first
Data is sent with the most significant bit first
0 RW Clock Edge for Setup/Sample
Mode Description
SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of
the bus clock in synchronous mode
SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of
the bus clock in synchronous mode
0 RW Clock Polarity
Mode Description
IDLELOW The bus clock used in synchronous mode has a low base value
Reference Manual
Rev. 1.1 | 564