Register Description - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

23.5 Register Description

23.5.1 VDACn_CTRL - Control Register
Offset
0x000
Reset
Access
Name
Bit Name
31 DACCLKMODE
Selects DAC clock source from synchronous or asynchronous - with respect to Peripheral Clock - clock source
Value
0
1
30:29 Reserved
28 WARMUPMODE
Select Warm-up Mode for DAC
Value
0
1
27:26 Reserved
25:24 REFRESHPERIOD
Select refresh counter period. A channel x will be refreshed with the period set in REFRESHPERIOD if the channel in
VDACn_CHxCTRL has its TRIGMODE set to REFRESH or SWREFRESH.
Value
0
1
2
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Reset Access Description
0 RW Clock Mode
Mode Description
SYNC Uses HFPERCLK to generate DAC_CLK, DAC will run with static set-
tings in EM2 in this mode
ASYNC Uses internal VDAC oscillator to generate DAC_CLK. DAC will be
available in EM2
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Warm-up Mode
Mode Description
NORMAL DAC is shut off after each sample off conversion
KEEPINSTANDBY DAC is kept in standby mode between sample off conversions
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Refresh Period
Mode Description
8CYCLES All channels with enabled refresh are refreshed every 8 DAC_CLK cy-
cles
16CYCLES All channels with enabled refresh are refreshed every 16 DAC_CLK cy-
cles
32CYCLES All channels with enabled refresh are refreshed every 32 DAC_CLK cy-
cles
Bit Position
Reference Manual
VDAC - Digital to Analog Converter
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 764