Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 388

Bit Name
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7:6 Reserved
5 CCV1TOP
When set, the counter wraps around on a CC1 event.
4 PRECCV0TOP
When set, the pre-counter wraps around when PRECNT equals RTCC_CC0_CCV[14:0].
3 Reserved
2 DEBUGRUN
Set this bit to keep the RTCC running during a debug halt.
Value
0
1
1 Reserved
0 ENABLE
Enable the RTCC.
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Reset Access Description
DIV4 CLK
DIV8 CLK
DIV16 CLK
DIV32 CLK
DIV64 CLK
DIV128 CLK
DIV256 CLK
DIV512 CLK
DIV1024 CLK
DIV2048 CLK
DIV4096 CLK
DIV8192 CLK
DIV16384 CLK
DIV32768 CLK
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW CCV1 Top Value Enable
0 RW Pre-counter CCV0 Top Value Enable
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Debug Mode Run Enable
Description
RTCC is frozen in debug mode
RTCC is running in debug mode
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW RTCC Enable
RTCC - Real Time Counter and Calendar
= LFECLK /4
CNT RTCC
= LFECLK /8
CNT RTCC
= LFECLK /16
CNT RTCC
= LFECLK /32
CNT RTCC
= LFECLK /64
CNT RTCC
= LFECLK /128
CNT RTCC
= LFECLK /256
CNT RTCC
= LFECLK /512
CNT RTCC
= LFECLK /1024
CNT RTCC
= LFECLK /2048
CNT RTCC
= LFECLK /4096
CNT RTCC
= LFECLK /8192
CNT RTCC
= LFECLK /16384
CNT RTCC
= LFECLK /32768
CNT RTCC
Reference Manual
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 388