Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 958

Bit Name
6
7
7 Reserved
6:4 LFPRESC
This bitfield is used to divide the clock to the low frequency timer
Value
0
1
2
3
4
5
6
7
3:2 Reserved
1:0 AUXPRESC
This bitfield is used to divide the clock to the high frequency timer
Value
0
1
2
3
silabs.com | Building a more connected world.
Reset Access Description
DIV64 The period counter clock frequency is LFACLK
DIV128 The period counter clock frequency is LFACLK
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Prescaling Factor for Low Frequency Timer
Mode Description
DIV1 Low frequency timer is clocked with LFACLK
DIV2 Low frequency timer is clocked with LFACLK
DIV4 Low frequency timer is clocked with LFACLK
DIV8 Low frequency timer is clocked with LFACLK
DIV16 Low frequency timer is clocked with LFACLK
DIV32 Low frequency timer is clocked with LFACLK
DIV64 Low frequency timer is clocked with LFACLK
DIV128 Low frequency timer is clocked with LFACLK
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Prescaling Factor for High Frequency Timer
Mode Description
DIV1 High frequency timer is clocked with AUXHFRCO/1
DIV2 High frequency timer is clocked with AUXHFRCO/2
DIV4 High frequency timer is clocked with AUXHFRCO/4
DIV8 High frequency timer is clocked with AUXHFRCO/8
LESENSE - Low Energy Sensor Interface
/64
LESENSE
/128
LESENSE
/1
LESENSE
/2
LESENSE
/4
LESENSE
/8
LESENSE
/16
LESENSE
/32
LESENSE
/64
LESENSE
/128
LESENSE
Reference Manual
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 958