I2Cn_Status - Status Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

17.5.4 I2Cn_STATUS - Status Register

Offset
0x00C
Reset
Access
Name
Bit Name
31:10 Reserved
9 RXFULL
Set when the receive buffer is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room
for one more frame in the receive shift register.
8 RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
7 TXBL
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
6 TXC
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmis-
sion starts.
5 PABORT
An abort is pending and will be transmitted as soon as possible.
4 PCONT
A continue is pending and will be transmitted as soon as possible.
3 PNACK
A not-acknowledge is pending and will be transmitted as soon as possible.
2 PACK
An acknowledge is pending and will be transmitted as soon as possible.
1 PSTOP
A stop condition is pending and will be transmitted as soon as possible.
0 PSTART
A start condition is pending and will be transmitted as soon as possible.
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 R RX FIFO Full
0 R RX Data Valid
1 R TX Buffer Level
0 R TX Complete
0 R Pending Abort
0 R Pending Continue
0 R Pending NACK
0 R Pending ACK
0 R Pending STOP
0 R Pending START
I2C - Inter-Integrated Circuit Interface
Bit Position
Reference Manual
1.2 Conven-
Rev. 1.1 | 509