Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 505

Bit Name
13:12 BITO
Use to generate a timeout when SCL has been high for a given amount time between a START and STOP condition. When
in a bus transaction, i.e. the BUSY flag is set, a timer is started whenever SCL goes high. When the timer reaches the value
defined by BITO, it sets the BITO interrupt flag. The BITO interrupt flag will then be set periodically as long as SCL remains
high. The bus idle timeout is active as long as BUSY is set. It is thus stopped automatically on a timeout if GIBITO is set. It
is also stopped a STOP condition is detected and when the ABORT command is issued. The timeout is activated whenever
the bus goes BUSY, i.e. a START condition is detected. The timeout value can be calculated by
Value
0
1
2
3
11:10 Reserved
9:8 CLHR
Determines the ratio between the low and high parts of the clock signal generated on SCL as master.
Value
0
1
2
7 TXBIL
Determines the interrupt and status level of the transmit buffer.
Value
0
1
6 GCAMEN
Set to enable address match on general call in addition to the programmed slave address.
Value
0
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Reset Access Description
0x0 RW Bus Idle Timeout
timeout = PCC/(f
Mode Description
OFF Timeout disabled
40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 50us timeout.
80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz,
this results in a 100us timeout.
160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100
kHz, this results in a 200us timeout.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Clock Low High Ratio
Mode Description
STANDARD The ratio between low period and high period counters (N
4:4
ASYMMETRIC The ratio between low period and high period counters (N
6:3
FAST The ratio between low period and high period counters (N
11:6
0 RW TX Buffer Interrupt Level
Mode Description
EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buf-
fer becomes empty. TXBL is cleared when the buffer becomes non-
empty.
HALFFULL TXBL status and the TXBL interrupt flag are set when the transmit buf-
fer goes from full to half-full or empty. TXBL is cleared when the buffer
becomes full.
0 RW General Call Address Match Enable
Description
General call address will be NACK'ed if it is not included by the slave
address and address mask.
I2C - Inter-Integrated Circuit Interface
x (N + N ))
SCL low high
Reference Manual
1.2 Conven-
:N ) is
low high
:N ) is
low high
:N ) is
low high
Rev. 1.1 | 505