Register Description; Ldma_Ctrl - Dma Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

Offset Name
0x1E4 LDMA_CH7_DST
0x1E8 LDMA_CH7_LINK

8.6 Register Description

8.6.1 LDMA_CTRL - DMA Control Register

Offset
0x000
Reset
Access
Name
Bit Name
31:27 Reserved
26:24 NUMFIXED
This field defines the number of Fixed Priority Arbitration channels. Channels CH0 though CH(n-1) are fixed, and channels
CH(n) through CH7 are round robin, where n is the field value. The reset value will give all fixed channels.
23:16 Reserved
15:8 SYNCPRSCLREN
Setting a bit in this field will enable the corresponding PRS input to clear the respective bit in the SYNCTRIG field of the
LDMA_SYNC register. Refer to the PRS section for a list of the PRS inputs.
7:0 SYNCPRSSETEN
Setting a bit in this field will enable the corresponding PRS input to set the respective bit in the SYNCTRIG field of the
LDMA_SYNC register. Refer to the PRS section for a list of the PRS inputs.
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Type Description
RWH Channel Descriptor Destination Data Address Register
RWH Channel Descriptor Link Structure Address Register
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x7 RW Number of Fixed Priority Channels
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x00 RW Synchronization PRS Clear Enable
0x00 RW Synchronization PRS Set Enable
Bit Position
Reference Manual
LDMA - Linked DMA Controller
1.2 Conven-
1.2 Conven-
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