Lesense_Idleconf - Gpio Idle Phase Configuration (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

28.5.17 LESENSE_IDLECONF - GPIO Idle Phase Configuration (Async Reg)

For more information about asynchronous registers see
Offset
0x040
Reset
Access
Name
Bit Name
31:30 CH15
This bitfield determines how the channel is configured during the idle phase
Value
0
1
2
3
29:28 CH14
This bitfield determines how the channel is configured during the idle phase
Value
0
1
2
3
27:26 CH13
This bitfield determines how the channel is configured during the idle phase
Value
0
1
2
3
25:24 CH12
This bitfield determines how the channel is configured during the idle phase
Value
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4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
0x0 RW Channel 15 Idle Phase Configuration
Mode Description
DISABLE CH15 output is disabled in idle phase
HIGH CH15 output is high in idle phase
LOW CH15 output is low in idle phase
DAC CH15 output is connected to VDAC output in idle phase. Note that this
mode is only available on channels 4, 5, 7, 10, 12, 13
0x0 RW Channel 14 Idle Phase Configuration
Mode Description
DISABLE CH14 output is disabled in idle phase
HIGH CH14 output is high in idle phase
LOW CH14 output is low in idle phase
DAC CH14 output is connected to VDAC output in idle phase. Note that this
mode is only available on channels 4, 5, 7, 10, 12, 13
0x0 RW Channel 13 Idle Phase Configuration
Mode Description
DISABLE CH13 output is disabled in idle phase
HIGH CH13 output is high in idle phase
LOW CH13 output is low in idle phase
DAC CH13 output is connected to VDAC output in idle phase. Note that this
mode is only available on channels 4, 5, 7, 10, 12, 13
0x0 RW Channel 12 Idle Phase Configuration
Mode Description
LESENSE - Low Energy Sensor Interface
Bit Position
Reference Manual
Registers).
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