Vdacn_Ch0Ctrl - Channel 0 Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

23.5.3 VDACn_CH0CTRL - Channel 0 Control Register

Offset
0x008
Reset
Access
Name
Bit Name
31:16 Reserved
15:12 PRSSEL
Select Channel 0 PRS input channel.
Value
0
1
2
3
4
5
6
7
8
9
10
11
11:9 Reserved
8 PRSASYNC
Set this bit to 1 to treat PRS channel as asynchronous
7 Reserved
6:4 TRIGMODE
Select Channel 0 conversion trigger.
Value
0
1
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Channel 0 PRS Trigger Select
Mode Description
PRSCH0 PRS ch 0 triggers a conversion.
PRSCH1 PRS ch 1 triggers a conversion.
PRSCH2 PRS ch 2 triggers a conversion.
PRSCH3 PRS ch 3 triggers a conversion.
PRSCH4 PRS ch 4 triggers a conversion.
PRSCH5 PRS ch 5 triggers a conversion.
PRSCH6 PRS ch 6 triggers a conversion.
PRSCH7 PRS ch 7 triggers a conversion.
PRSCH8 PRS ch 8 triggers a conversion.
PRSCH9 PRS ch 9 triggers a conversion.
PRSCH10 PRS ch 10 triggers a conversion.
PRSCH11 PRS ch 11 triggers a conversion.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Channel 0 PRS Asynchronous Enable
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Channel 0 Trigger Mode
Mode Description
SW Channel 0 is triggered by CH0DATA or COMBDATA write
PRS Channel 0 is triggered by PRS input
Bit Position
Reference Manual
VDAC - Digital to Analog Converter
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 769