Wdogn_Pchx_Prsctrl - Prs Control Register (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

14.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg)

For more information about asynchronous registers see
Offset
0x00C
Reset
Access
Name
Bit Name
31:9 Reserved
8 PRSMISSRSTEN
When set, a PRS missing event will trigger a watchdog reset.
7:4 Reserved
3:0 PRSSEL
These bits select the PRS input for the PRS channel.
Value
0
1
2
3
4
5
6
7
8
9
10
11
silabs.com | Building a more connected world.
4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW PRS Missing Event Will Trigger a Watchdog Reset
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW PRS Channel PRS Select
Mode Description
PRSCH0 PRS Channel 0 selected as input
PRSCH1 PRS Channel 1 selected as input
PRSCH2 PRS Channel 2 selected as input
PRSCH3 PRS Channel 3 selected as input
PRSCH4 PRS Channel 4 selected as input
PRSCH5 PRS Channel 5 selected as input
PRSCH6 PRS Channel 6 selected as input
PRSCH7 PRS Channel 7 selected as input
PRSCH8 PRS Channel 8 selected as input
PRSCH9 PRS Channel 9 selected as input
PRSCH10 PRS Channel 10 selected as input
PRSCH11 PRS Channel 11 selected as input
Bit Position
Reference Manual
WDOG - Watchdog Timer
Registers).
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 415