Wdog_Syncbusy - Synchronization Busy Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

14.5.3 WDOG_SYNCBUSY - Synchronization Busy Register

Offset
0x008
Reset
Access
Name
Bit Name
31:4 Reserved
3 PCH1_PRSCTRL
Set when the value written to PCH1_PRSCTRL is being synchronized.
2 PCH0_PRSCTRL
Set when the value written to PCH0_PRSCTRL is being synchronized.
1 CMD
Set when the value written to CMD is being synchronized.
0 CTRL
Set when the value written to CTRL is being synchronized.
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 R PCH1_PRSCTRL Register Busy
0 R PCH0_PRSCTRL Register Busy
0 R CMD Register Busy
0 R CTRL Register Busy
Bit Position
Reference Manual
WDOG - Watchdog Timer
1.2 Conven-
Rev. 1.1 | 414