Register Map - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

18.4 Register Map

The offset register address is relative to the registers base address.
Offset Name
0x000 USARTn_CTRL
0x004 USARTn_FRAME
0x008 USARTn_TRIGCTRL
0x00C USARTn_CMD
0x010 USARTn_STATUS
0x014 USARTn_CLKDIV
0x018 USARTn_RXDATAX
0x01C USARTn_RXDATA
0x020 USARTn_RXDOUBLEX
0x024 USARTn_RXDOUBLE
0x028 USARTn_RXDATAXP
0x02C USARTn_RXDOUBLEXP
0x030 USARTn_TXDATAX
0x034 USARTn_TXDATA
0x038 USARTn_TXDOUBLEX
0x03C USARTn_TXDOUBLE
0x040 USARTn_IF
0x044 USARTn_IFS
0x048 USARTn_IFC
0x04C USARTn_IEN
0x050 USARTn_IRCTRL
0x058 USARTn_INPUT
0x05C USARTn_I2SCTRL
0x060 USARTn_TIMING
0x064 USARTn_CTRLX
0x068 USARTn_TIMECMP0
0x06C USARTn_TIMECMP1
0x070 USARTn_TIMECMP2
0x074 USARTn_ROUTEPEN
0x078 USARTn_ROUTELOC0
0x07C USARTn_ROUTELOC1
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Type Description
RW Control Register
RW USART Frame Format Register
RW USART Trigger Control Register
W1 Command Register
R USART Status Register
RWH Clock Control Register
R(a) RX Buffer Data Extended Register
R(a) RX Buffer Data Register
R(a) RX Buffer Double Data Extended Register
R(a) RX FIFO Double Data Register
R RX Buffer Data Extended Peek Register
R RX Buffer Double Data Extended Peek Register
W TX Buffer Data Extended Register
W TX Buffer Data Register
W TX Buffer Double Data Extended Register
W TX Buffer Double Data Register
R Interrupt Flag Register
W1 Interrupt Flag Set Register
(R)W1 Interrupt Flag Clear Register
RW Interrupt Enable Register
RW IrDA Control Register
RW USART Input Register
RW I2S Control Register
RW Timing Register
RW Control Register Extended
RW Used to Generate Interrupts and Various Delays
RW Used to Generate Interrupts and Various Delays
RW Used to Generate Interrupts and Various Delays
RW I/O Routing Pin Enable Register
RW I/O Routing Location Register
RW I/O Routing Location Register
Reference Manual
Rev. 1.1 | 561